Abstract: A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

Abstract: In a multi-threading microprocessor, a queue for a scarce resource such as a multiplier alternates on a fine-grained basis between instructions in various threads. When a long-latency instruction is discovered in a thread, the instructions in that thread that depend on the latency are flushed out of the thread until the latency is resolved, with the instructions in other threads filling empty slots from the thread waiting for the long-latency instruction and continuing to execute without being delayed by having to wait for the long-latency instruction.