Patents by Inventor Victor Shumilin

Victor Shumilin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Handling potential deadlocks and correctness problems of reduce operations in parallel systems
    Patent number: 8621484
    Abstract: In one embodiment, the present invention includes a method for executing a first reduction operation on data in an input buffer, executing a second reduction operation on the data, where the second reduction operation has a higher reliability than the first reduction operation, and comparing the first and second results. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Patrick Ohly, Victor Shumilin
  • Handling potential deadlocks and correctness problems of reduce operations in parallel systems
    Publication number: 20090064176
    Abstract: In one embodiment, the present invention includes a method for executing a first reduction operation on data in an input buffer, executing a second reduction operation on the data, where the second reduction operation has a higher reliability than the first reduction operation, and comparing the first and second results. Other embodiments are described and claimed.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Inventors: Patrick Ohly, Victor Shumilin