Abstract: An apparatus generally comprising a circuit and an interface device is disclosed. The circuit may be configured to (i) generate a plurality of test signals to simultaneously stimulate a device and a model of the device during a test and (ii) receive a plurality of model signals generated by the model in response to the test signals. The interface device may be configured to receive a plurality of device signals generated by the device in response the test signals.

Abstract: A microcontroller power management system wherein the voltage of a power supply is monitored and the microcontroller central processing unit ("CPU") receives an interrupt signal when the supply voltage falls below a predetermined level. The CPU monitors the duration of the low voltage condition and switches into a sleep mode, after storing any data in its registers that are not maintained in the sleep mode, when that duration exceeds a fixed limit that indicates more than a temporary power glitch is being experienced. If only a short power glitch, the CPU continues normal operation. A large capacitor connected to the power supply input to the microcontroller provides enough energy for the microcontroller to operate normally during short glitches and to operate in a sleep mode for a considerable time, thereby maintaining data in CMOS static RAM until power is restored.