Abstract: An emulator uses code translation and recompilation to execute target computer system applications on a host computer system. Target application code is partitioned into target application code blocks, and related target application code blocks are combined into block groups and translated. Translated application code block groups are sized to comply with restrictions on branch instruction size. Upon selecting an application code block group for execution, a cache tag is used to determine if a corresponding translated code block group is available and valid. If not, the block group is translated and executed. Sequentially executed translated code blocks are located in adjacent portions of memory to improve performance when switching between translated code blocks. The emulator may use a link register of the host computer system to prefetch instructions and data from translated code blocks. The emulator also takes into account structural hazards in translating instructions.

Abstract: A method and apparatus for processor emulation using speculative forward translation are disclosed. A potential candidate for forward translation is identified from one or more portions of target system code. A priority for forward translation is assigned to the potential candidate. It is determined whether the potential candidate is a valid candidate for forward translation. If valid, the potential candidate is translated with a host system to produce one or more corresponding blocks of translated code executable by the host system.

Abstract: In one embodiment, the methods and apparatuses detect content that represents original image information; detect a direction of the content wherein the direction corresponds to a portion of the original image information; compare a variation between adjacent pixels that are represented by the original image information; and generate new image information based on the direction of the content and the variation between the adjacent pixels.

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract: Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is interpreted to generate interpreted code instructions that emulate a first component on the host system. A second set of code instructions is translated to generate translated code instructions that emulate a second component of the target system on the host system. The interpreted instructions, are executed based on a first clock (which may be a fixed clock) and the translated instructions are executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the translated or interpreted instructions or a memory access to maintain a desired synchronization between the translated instructions and the interpreted instructions.

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract: Thread switching prevents pipeline stalls when executing multiple threads. An analysis of a first thread identifies instructions capable of causing pipeline stalls. If pipeline stalls from the identified instructions are likely, thread switching instructions are added to the first thread in place of the identified instructions. Thread switching instructions direct a microprocessor to suspend executing the thread and begin executing a second thread. Thread switching instructions can be added to the second thread to enable the resumption of the first thread at the location specified by the identified instruction. The thread switching instructions are configured to avoid pipeline stalls when switching threads. Thread switching instructions can store and retrieve thread-specific information upon the suspension and resumption of threads. Thread switching instructions can schedule the execution of two or more threads in accordance with load balancing schemes.