Abstract: Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

Abstract: An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to generate a second intermediate signal by delaying the first intermediate signal by inserting one of a plurality of fixed delays in response to a first control signal. The second delay circuit may be configured to generate the output signal by delaying the second intermediate signal by inserting a programmable delay in response to a second control signal.

Abstract: An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to generate a second intermediate signal by delaying the first intermediate signal by inserting one of a plurality of fixed delays in response to a first control signal. The second delay circuit may be configured to generate the output signal by delaying the second intermediate signal by inserting a programmable delay in response to a second control signal.

Abstract: Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

Abstract: Systems and methods are provided for latching a data signal. In one embodiment, a system comprises a first delay circuit that programmably delays a strobe signal with a first delay to latch a data signal. The system also comprises a second delay circuit that receives the data signal and delays the data signal with a second delay that is substantially inherent to the first delay. The system may include a logic circuit coupled between the first and the second delay circuits for latching the data signal in substantial alignment with the strobe signal. In one embodiment, similar delays are used in a master delay circuit, while in another embodiment such delays are used in slave devices connected to a master delay circuit.