Patents by Inventor Victor Sutcliffe
Victor Sutcliffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8860147Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.Type: GrantFiled: November 26, 2007Date of Patent: October 14, 2014Assignee: Texas Instruments IncorporatedInventors: Amitava Chatterjee, Howard Tigelaar, Victor Sutcliffe
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Patent number: 7728436Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.Type: GrantFiled: January 9, 2008Date of Patent: June 1, 2010Assignees: IMEC, Texas Instruments Inc.Inventors: Caroline Whelan, Victor Sutcliffe
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Publication number: 20090134471Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.Type: ApplicationFiled: November 26, 2007Publication date: May 28, 2009Inventors: Amitava Chatterjee, Howard Tigelaar, Victor Sutcliffe
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Publication number: 20080105979Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.Type: ApplicationFiled: January 9, 2008Publication date: May 8, 2008Applicants: Interuniversitair Microelektronica Centrum (IMEC), Texas Instruments Inc.Inventors: Caroline Whelan, Victor Sutcliffe
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Patent number: 7368377Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.Type: GrantFiled: December 7, 2005Date of Patent: May 6, 2008Assignees: Interuniversitair Microelektronica Centrum (IMEC) vzw, Texas Instruments Inc.Inventors: Caroline Whelan, Victor Sutcliffe
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Patent number: 7319274Abstract: Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer including an interconnect structure, where the dielectric layer is formed of a dielectric material including Si, C and O. The damascene stack also includes a converted portion of the dielectric layer, where the converted portion is adjacent to the at least one interconnect structure and has a lower carbon content than the dielectric material. The damascene stack also includes an airgap formed adjacent to the interconnect structure, the airgap being formed by removing at least part of the converted portion using an etch compound.Type: GrantFiled: March 22, 2006Date of Patent: January 15, 2008Assignee: Interuniversitair Microelektronica Centrum (IMEC v2w)Inventors: Gerald Beyer, Jean Paul Gueneau de Mussy, Karen Maex, Victor Sutcliffe
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Publication number: 20060177990Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.Type: ApplicationFiled: March 22, 2006Publication date: August 10, 2006Applicants: Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.Inventors: Gerald Beyer, Jean Paul Mussy, Karen Maex, Victor Sutcliffe
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Patent number: 7078352Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.Type: GrantFiled: September 30, 2004Date of Patent: July 18, 2006Assignees: Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.Inventors: Gerald Beyer, Jean Paul Gueneau de Mussy, Karen Maex, Victor Sutcliffe
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Publication number: 20060128142Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.Type: ApplicationFiled: December 7, 2005Publication date: June 15, 2006Inventors: Caroline Whelan, Victor Sutcliffe
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Publication number: 20050074961Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.Type: ApplicationFiled: September 30, 2004Publication date: April 7, 2005Applicants: Interuniversitair Microelektronica Centrum (IMEC vzw), Texas Instruments, Inc.Inventors: Gerald Beyer, Jean Gueneau de Mussy, Karen Maex, Victor Sutcliffe
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Publication number: 20050012558Abstract: The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.Type: ApplicationFiled: August 18, 2004Publication date: January 20, 2005Inventors: Andrew Marshall, Victor Sutcliffe