Patents by Inventor Victor Szeto

Victor Szeto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compression of high dynamic ratio fields for machine learning
    Patent number: 11405052
    Abstract: Various embodiments include methods and devices for implementing decompression of compressed high dynamic ratio fields. Various embodiments may include receiving compressed first and second sets of data fields, decompressing the first and second compressed sets of data fields to generate first and second decompressed sets of data fields, receiving a mapping for mapping the first and second decompressed sets of data fields to a set of data units, aggregating the first and second decompressed sets of data fields using the mapping to generate a compression block comprising the set of data units.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: August 2, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Clara Ka Wah Sung, Meghal Varia, Serag Gadelrab, Cheng-Teh Hsieh, Jason Edward Podaima, Victor Szeto, Richard Boisjoly, Milivoje Aleksic, Tom Longo, In-Suk Chong
  • Compression Of High Dynamic Ratio Fields For Machine Learning
    Publication number: 20210288660
    Abstract: Various embodiments include methods and devices for implementing decompression of compressed high dynamic ratio fields. Various embodiments may include receiving compressed first and second sets of data fields, decompressing the first and second compressed sets of data fields to generate first and second decompressed sets of data fields, receiving a mapping for mapping the first and second decompressed sets of data fields to a set of data units, aggregating the first and second decompressed sets of data fields using the mapping to generate a compression block comprising the set of data units.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Clara Ka Wah SUNG, Meghal VARIA, Serag GADELRAB, Cheng-Teh HSIEH, Jason Edward PODAIMA, Victor SZETO, Richard BOISJOLY, Milivoje ALEKSIC, Tom LONGO, In-Suk CHONG
  • Compression of high dynamic ratio fields for machine learning
    Patent number: 11025271
    Abstract: Various embodiments include methods and devices for implementing compression of high dynamic ratio fields. Various embodiments may include receiving a compression block having data units, receiving a mapping for the compression block, wherein the mapping is configured to map bits of each data unit to two or more data fields to generate a first set of data fields and a second set of data fields, compressing the first set of data fields together to generate a compressed first set of data fields, and compressing the second set of data fields together to generate a compressed second set of data fields.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: June 1, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Clara Ka Wah Sung, Meghal Varia, Serag Gadelrab, Cheng-Teh Hsieh, Jason Edward Podaima, Victor Szeto, Richard Boisjoly, Milivoje Aleksic, Tom Longo, In-Suk Chong
  • Compression Of High Dynamic Ratio Fields For Machine Learning
    Publication number: 20200274549
    Abstract: Various embodiments include methods and devices for implementing compression of high dynamic ratio fields. Various embodiments may include receiving a compression block having data units, receiving a mapping for the compression block, wherein the mapping is configured to map bits of each data unit to two or more data fields to generate a first set of data fields and a second set of data fields, compressing the first set of data fields together to generate a compressed first set of data fields, and compressing the second set of data fields together to generate a compressed second set of data fields.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 27, 2020
    Inventors: Clara Ka Wah SUNG, Meghal VARIA, Serag GADELRAB, Cheng-Teh HSIEH, Jason Edward PODAIMA, Victor SZETO, Richard BOISJOLY, Milivoje ALEKSIC, Tom LONGO, In-Suk CHONG
  • Single SDIO interface with multiple SDIO units
    Patent number: 10127172
    Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 13, 2018
    Assignee: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
    Inventors: Victor Szeto, Steven McBirnie
  • Multiple access single SDIO interface with multiple SDIO units
    Patent number: 9830280
    Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator. In some configurations, a single multiple SDIO (MSDIO) command may cause two or more SDIO units to return data to a host.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 28, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Klauss Riess, Victor Szeto, Gary Hum
  • Single relay SDIO interface with multiple SDIO units
    Patent number: 9811485
    Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: November 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Victor Szeto
  • Single SDIO Interface with Multiple SDIO Units
    Publication number: 20160371214
    Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventors: Victor Szeto, Steven McBirnie
  • Single Relay SDIO Interface with Multiple SDIO Units
    Publication number: 20160371209
    Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventor: Victor Szeto
  • Multiple Access Single SDIO Interface with Multiple SDIO Units
    Publication number: 20160371203
    Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator. In some configurations, a single multiple SDIO (MSDIO) command may cause two or more SDIO units to return data to a host.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventors: Klaus Riess, Victor Szeto, Gary Hum