Abstract: Automated External Defibrillator (AED) devices may include a high voltage capacitor (HV Cap) configured to store energy required to deliver a defibrillation shock to a patient; batteries configured to charge the HV Cap; a DC/DC converter circuit including a high voltage transformer, a FET switch with associated driver, and a rectifying diode; an H-bridge circuit configured to transform energy released from the HV Cap into a bi-phasic pulse; and a memory and microprocessor configured to operate the AED device. In particular, the HV Cap, the DC/DC converter circuit, the H-bridge circuit, the one or more batteries, and the memory and the microprocessor may contained in a pocket-sized housing, the AED device may be configured to continuously monitor and adjust the rate at which the batteries charge the HV Cap, and the AED device may include a variable frequency relaxation oscillator circuit configured to acquire a patients Z-body measurement.

Abstract: Automated External Defibrillator (AED) devices may include a high voltage capacitor (HV Cap) configured to store energy required to deliver a defibrillation shock to a patient; batteries configured to charge the HV Cap; a DC/DC converter circuit including a high voltage transformer, a FET switch with associated driver, and a rectifying diode; an H-bridge circuit configured to transform energy released from the HV Cap into a bi-phasic pulse; and a memory and microprocessor configured to operate the AED device. In particular, the HV Cap, the DC/DC converter circuit, the H-bridge circuit, the one or more batteries, and the memory and the microprocessor may contained in a pocket-sized housing, the AED device may be configured to continuously monitor and adjust the rate at which the batteries charge the HV Cap, and the AED device may include a variable frequency relaxation oscillator circuit configured to acquire a patients Z-body measurement.

Abstract: A two part connector for the temporary connection of an external periphery device to a printed circuit board (PCB). When coding or diagnostics need to be performed on much of todays electronic or electronic controlled equipment, an external unit needs to be physically connected to the microprocessor on the PCB of the equipment. Until now equipment manufacturers either install a socket onto the PCB, or form a mating part of connector directly on the surface of PCB, that is electronically connected to the microprocessor through electrical trace paths. This device eliminates the need for a socket and forms an intermediary element between the external unit and the PCB, that connects to the PCB with a set of vertical pins that matingly connect to a series of cutouts on the PCB. This device connects to a plethora of external devices and takes zero space on the surface of the PCB.

Abstract: A two part connector for the temporary connection of an external periphery device to a printed circuit board (PCB). When coding or diagnostics need to be performed on much of todays electronic or electronic controlled equipment, an external unit needs to be physically connected to the microprocessor on the PCB of the equipment. Until now equipment manufacturers either install a socket onto the PCB, or form a mating part of connector directly on the surface of PCB, that is electronically connected to the microprocessor through electrical trace paths. This device eliminates the need for a socket and forms an intermediary element between the external unit and the PCB, that connects to the PCB with a set of vertical pins that matingly connect to a series of cutouts on the PCB. This device connects to a plethora of external devices and takes zero space on the surface of the PCB.

Abstract: The present invention relates to a microprocessor controlled battery management system that optimizes the total electrical capacity of that battery. It uses localized cell power sources that correct the capacity of the individual connected cells to achieve the maximum capacity of the battery as it acts in a synergistic series connection of cells. The microprocessor retrieves data of battery load current, cell voltage, cell temperature, and battery charger current in timed increments. Through the application of the microprocessor's algorithms, after an initial cell profiling of individual cell capacities has been performed, individual cell DC/DC converters are enabled to correct the condition of the individual cells. In this manner the battery capacity is not affected by the capacity of the weakest cell.

Abstract: A fixture for holding an integrated circuit. The integrated circuit is of the type having a front side and an opposing back side. The fixture positions the integrated circuit for simultaneously electrically probing and viewing both the front side and the back side of the integrated circuit. A supporting brace provides a support that is immobile in at least a first direction, against which to cooperatively brace the integrated circuit. A first jaw piece is disposed adjacent the supporting brace. The first jaw piece has a vee shape for receiving a first corner of the integrated circuit and cooperatively aligns the integrated circuit into a position for simultaneously electrically probing and viewing the front side and the back side of the integrated circuit. An adjustable brace provides a movable second position in the first direction relative to the supporting brace, against which to cooperatively brace the integrated circuit with the supporting brace.

Abstract: A fixture for holding a semiconductor chip during a polishing process can be made to also hold the chip while the chip is inspected by a scanning electron microscope. In this manner, the polishing of the chip may be inspected and monitored without removing the chip from the polishing fixture. This allows polishing to be resumed, if necessary, with more precision. This results because the position of the chip with respect to the polishing fixture has not been altered by removing and then resecuring the chip as would be otherwise necessary for microscopic inspection of the chip.

Abstract: An improved method of deprocessing semiconductor chips provides faster, more accurate and more complete deprocessing. The chip to be deprocessed is placed in a chemical agent to loosen or undercut layers of material to be removed. A physical impact or series of impacts is then delivered to the chip, for example, by a compression wave transmitted through a fluid medium. The impact will cause chemically loosened or undercut material to break loose from the chip. The amount of time between when the chip is placed in the chemical agent and when the impact occurs, and the power and duration of the impact can be controlled to determine what layer of the chip structure will be exposed by the deprocessing.

Abstract: A fixture for holding a semiconductor chip during a polishing process can be made to also hold the chip while the chip is inspected by a scanning electron microscope. In this manner, the polishing of the chip may be inspected and monitored without removing the chip from the polishing fixture. This allows polishing to be resumed, if necessary, with more precision. This results because the position of the chip with respect to the polishing fixture has not been altered by removing and then resecuring the chip as would be otherwise necessary for microscopic inspection of the chip.

Abstract: A reconfigurable array of test structures for testing portions of a semiconductor device, comprising a plurality of probe pads, comprising a first probe pad and a remainder of probe pads, at least one of which remainder of probe pads is a common lead; to each of said plurality of probe pads, except for said common lead, are attached two conductors; in each of which said two conductors is connected a test structure, a first end of which semiconductor device is connected to said conductor and a second end of which test structure is connected to said common lead, except for said first probe pad, for which first probe pad only a test structure is connected in the first conductor of the two conductors and a fusible link in the second conductor of the two conductors connected to said common lead; wherein one of each of said two conductors contains a fusible link connected in series with said test structure; and a method for testing portions of a semiconductor device employing such a reconfigurable array of test str

Abstract: A test apparatus for determining alignment of an implantation mask in the construction of thin film transistors (TFTs), a method for determining the alignment of an implantation mask employed in the construction of TFTs, and a method for constructing TFTs, employing a test implantation mask for the construction of an implantation region for multiple adjacent TFTs, are provided in which the test implantation mask has a sloped or stepped profile such that the masked area increases as the test implantation mask extends from one TFT to another TFT.