Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

Abstract: An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs until the corresponding carry signals have reached their final values, which is achieved by adding a synchronization circuitry to the sum calculation path.

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

Abstract: A two's complement multiplier is combined with additional circuit elements to provide a multiplier capable of multiplication of two operands represented in any combination of either two's complement (signed) or unsigned magnitude formats, without increasing the size of the multiplier compared a multiplier for both operands represented in the same format; achieving the additional capability by providing independent inversion control to the partial product elements in the left column and the bottom row of the multiplier array, and controlling the generation of the carry-in signal to the carry propagate adder that performs the final addition of the partial products.

Abstract: A latch suitable for an integrated circuit having a test mechanism that involves scanning a set of logic circuits has a two-stage main latch and a level-sensitive scan latch, the combination operating normally as a single-phase latch and as a master-slave latch during scan mode. The scan mechanism is introduced at the second stage of the main latch, with the result that the capacitance introduced by the scan connection switches at most once per clock cycle, reducing the power load of the circuit; and the scan latch output is separated from the data output of the main latch, thereby further reducing the power load.

Abstract: A low-power integrated circuit containing a set of scan latches for passing data from flip-flops to test circuitry is modified such that the scan latches are formed from low-leakage transistors connected directly to the power supply so that they remain on during power-down and such that there is a data return path from the scan latches back to the flip-flops, so that the scan latches receive data from the flip-flops before a power-down mode, retain the data during power-down and return the data after power-down, thus saving on circuit area by using the scan latches for a second function. Further area is saved by using the scan trigger input to the flip-flops also for the data return path.

Abstract: An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs until the corresponding carry signals have reached their final values, which is achieved by adding a synchronization circuitry to the sum calculation path.