Patents by Inventor Victor Verdugo

Victor Verdugo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12087723
    Abstract: A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: September 10, 2024
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Victor Verdugo, Katrin Schmidt, Steffen Schmidt, Markus Schmitt
  • Publication number: 20230197674
    Abstract: A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body.
    Type: Application
    Filed: February 17, 2023
    Publication date: June 22, 2023
    Inventors: Victor Verdugo, Katrin Schmidt, Steffen Schmidt, Markus Schmitt
  • Patent number: 11610861
    Abstract: A method of soldering elements together includes providing a substrate having a metal die attach surface, providing a semiconductor die that is configured as a power semiconductor device and having a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack having a front side metallization and a contaminant protection layer, arranging the semiconductor die on the substrate with a region of solder material between the die attach surface and the rear side metallization, and performing a soldering process that reflows the region of solder material to form a soldered joint between the metal die attach surface and the rear side metallization, wherein the soldering process comprises applying mechanical pressure to the front side metallization.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 21, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Victor Verdugo, Katrin Schmidt, Steffen Schmidt, Markus Schmitt
  • Publication number: 20220084981
    Abstract: A method of soldering elements together includes providing a substrate having a metal die attach surface, providing a semiconductor die that is configured as a power semiconductor device and having a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack having a front side metallization and a contaminant protection layer, arranging the semiconductor die on the substrate with a region of solder material between the die attach surface and the rear side metallization, and performing a soldering process that reflows the region of solder material to form a soldered joint between the metal die attach surface and the rear side metallization, wherein the soldering process comprises applying mechanical pressure to the front side metallization, and wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body after the soldering process is completed.
    Type: Application
    Filed: September 14, 2020
    Publication date: March 17, 2022
    Inventors: Victor Verdugo, Katrin Schmidt, Steffen Schmidt, Markus Schmitt
  • Publication number: 20120204930
    Abstract: A thin-layer solar module includes a plurality of interconnected solar cells, having in the order indicated the layers (a) a substrate 3; (b) a first electrode layer 4; (c) a semiconductor layer 5; and (d) a second electrode layer 6. At least one non-linear recess is disposed in the first electrode layer and a second non-linear recess is disposed in the second electrode layer and in the semiconductor layer, wherein a first projection of the first non-linear recess onto the substrate 3 and a second projection 10 of the second non-linear recess onto the substrate intersect or contact each other at least two projection points. The thin-layer solar module has at least one island-shaped contact region extending in a direction vertical to the substrate through the layers (a) through (d). A third recess is present in the semiconductor layer 5 within the island-shaped contact region 11 and is filled with an electrically conductive material.
    Type: Application
    Filed: July 20, 2010
    Publication date: August 16, 2012
    Applicant: Q-CELLS SE
    Inventor: Victor Verdugo
  • Publication number: 20090098701
    Abstract: The present invention provides a method of manufacturing an integrated circuit comprising the steps of: providing a semiconductor substrate, etching at least one trench into a surface of said semiconductor substrate, performing an ion implantation step, wherein a direction of said ion implantation step is parallel to a vertical centre line of said trench, and performing a single oxidation step to form a first oxide layer with a first layer thickness covering a bottom of said at least one trench and a second oxide layer with a second layer thickness covering the sidewalls of said at least one trench, wherein said first layer thickness differs from said second layer thickness.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 16, 2009
    Inventors: Jurgen Faul, Martin Popp, Andrew Graham, Dongping Wu, Victor Verdugo
  • Publication number: 20090057810
    Abstract: A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section after generating the conductive structure.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 5, 2009
    Inventors: Victor Verdugo, Dongping Wu, Clemens Fitz