Abstract: A system and method for maintaining the integrity of data in a storage system. The method includes receiving a plurality of blocks of data having a predetermined multiple-block error detecting code; reading each block of the blocks of data; generating, for each block of data, an information-containing portion including an individual error detecting code for the block of data; and storing each block of data and each corresponding information-containing portion.

Abstract: A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.

Abstract: The invention is directed to techniques that include an error detection code (e.g., a CRC code) and cleared bytes (e.g., zeroes) with data (e.g., CKD data). The use of cleared bytes with CKD data enables detection of corrupt CKD data by simply generating a CRC code based on an entire data block and comparing that generated CRC code with an initial CRC code appended to the CKD data within that data block. One arrangement of the invention is directed to a data storage system that includes a circuit having a memory pipeline that receives a stream of data elements, and provides a series of byte groups that includes the stream of data elements, an error detection code and a set of cleared bytes to a set of storage devices. Each of the series of byte groups provided by the memory pipeline has a same byte width. The inclusion of the error detection code and the set of cleared bytes enables consistent alignment of each byte group in the series.

Abstract: A system having a plurality of processors, each one of the processors being adapted to issue a control signal and a processor ID code. Each one of the processors has: a unique, pre-assigned processor ID code, and a common software program. The software program operates to: receive the control signal and the processor ID code from the issuing one of the processors along with an indication of the one of the processors which issued the particular control signal and processor ID code; and test whether the received processor ID code is the same as the processor issuing the command and if so, generate one of the broadcast mode or uni-cast modes; otherwise, generate the other one of the broadcast or uni-cast modes.

Abstract: A method and apparatus for controlling the flow of data through director elements of a disk drive controller are responsive to external clock signals to synchronize the internal clock timing of each director. The external clock signals are available over either a first master bus or a secondary master bus, each of the buses being connected to the director element. Each director element has circuitry which monitors the occurrence of clock pulses over the buses as well as circuitry for switching, upon the occurrence of a failure of clock pulses on the master bus, from the master bus to the secondary bus for the receipt and resynchronization of clock pulses.

Abstract: A hardware emulation controller permits a high performance processor to be used with system circuitry that is configured for operation with a different processor. The hardware emulation controller is capable of modifying signals from the high performance processor for compatibility with the system circuitry. The hardware emulation controller is also capable of modifying signals from the system circuitry for compatibility with the high performance processor.

Abstract: A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.

Abstract: A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface includes a system memory comprising a pair of system memory sections. Each one of the system memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A pair of system busses is provided, each one of the pair of system busses being coupled to a corresponding one of the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus. The directors are configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory.

Abstract: A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.

Abstract: The invention is directed to techniques that include an error detection code (e.g., a CRC code) and cleared bytes (e.g., zeroes) with data (e.g., CKD data). The use of cleared bytes with CKD data enables detection of corrupt CKD data by simply generating a CRC code based on an entire data block and comparing that generated CRC code with an initial CRC code appended to the CKD data within that data block. One arrangement of the invention is directed to a data storage system that includes a circuit having a memory pipeline that receives a stream of data elements, and provides a series of byte groups that includes the stream of data elements, an error detection code and a set of cleared bytes to a set of storage devices. Each of the series of byte groups provided by the memory pipeline has a same byte width. The inclusion of the error detection code and the set of cleared bytes enables consistent alignment of each byte group in the series.

Abstract: A method and a control device is provided for upgrading computer system hardware, for example, on a printed circuit board, with system revision information. The method includes receiving, a serial data stream having data bits associated with the system revision information through a serial input of the control device, determining the start of the data bits, and storing at least a portion of the data bits associated with the system revision information within a read-only register of the control device.