Patents by Inventor Victor Wai Ner Tung

Victor Wai Ner Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Redundant writing of data to cached storage system
    Patent number: 5890219
    Abstract: An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. Each control processor is responsible for 2 pipelines and respective Direct Multiple Access (DMA) and Direct Single Access (DSA) pipelines, for Global Memory access. Each processor has its own Memory Data Register (MDR) to support DMA/DSA activity. The dual processors each access independent control store RAM, but run the same processor independent control program using an implementation that makes the hardware appear identical from both the X and Y processor sides. Pipelines are extended to add greater depth by incorporating a prefetch mechanism that permits write data to be put out to transceivers awaiting bus access, while two full buffers of assembled memory data are stored in Dual Port Ram and memory data words are assembled in pipeline gate arrays for passing to DPR.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: March 30, 1999
    Assignee: EMC Corporation
    Inventors: Stephen Lawrence Scaringella, Gal Sne, Victor Wai Ner Tung
  • High performance integrated cached storage device
    Patent number: 5890207
    Abstract: An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. Each control processor is responsible for 2 pipelines and respective Direct Multiple Access (DMA) and Direct Single Access (DSA) pipelines, for Global Memory access. Each processor has its own Memory Data Register (MDR) to support DMA/DSA activity. The dual processors each access independent control store RAM, but run the same processor independent control program using an implementation that makes the hardware appear identical from both the X and Y processor sides. Pipelines are extended to add greater depth by incorporating a prefetch mechanism that permits write data to be put out to transceivers awaiting bus access, while two full buffers of assembled memory data are stored in Dual Port Ram and memory data words are assembled in pipeline gate arrays for passing to DPR.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: March 30, 1999
    Assignee: EMC Corporation
    Inventors: Gal Sne, Victor Wai Ner Tung, Stephen Lawrence Scaringella
  • Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource
    Patent number: 5884055
    Abstract: An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. The dual processors each access independent control store RAM, but run the same processor independent control program using an implementation that makes the hardware appear identical from both the X and Y processor sides.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: March 16, 1999
    Assignee: EMC Corporation
    Inventors: Victor Wai Ner Tung, Gal Sne, Stephen Lawrence Scaringella