Patents by Inventor Victor Wong

Victor Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070248931
    Abstract: A method for caries detection uses an image capture device (30, 32) to obtain fluorescence image data from the tooth (20) by illuminating the tooth to excite fluorescent emission. A first enhanced image of the tooth is then obtained by illuminating the tooth at a first incident angle, obtaining a back-scattered reflectance image data from the tooth tissue, and combining the back-scattered reflectance image data with the fluorescence image data. A second enhanced image of the tooth is then obtained by illuminating the tooth at a second incident angle, obtaining a back-scattered reflectance image data from the tooth tissue, and combining the back-scattered reflectance image data with the fluorescence image data. The first and second enhanced images are then analyzed to select and display the best-contrast image. This method provides high contrast images for carious regions (58) on all tooth surfaces.
    Type: Application
    Filed: April 21, 2006
    Publication date: October 25, 2007
    Inventors: Victor Wong, Rongguang Liang, Michael Marcus, Paul McLaughlin, David Patton
  • Patent number: 7236385
    Abstract: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: June 26, 2007
    Assignee: Micron Technology, Inc.
    Inventors: J. Wayne Thompson, Jeffrey P. Wright, Victor Wong, Jim Cullum
  • Publication number: 20070114425
    Abstract: An x-ray imaging source comprises a radiation source (12) providing x-ray radiation. A substrate comprised of a scintillating material (16) responsive to a level of incident radiation provides output light according to the level of incident radiation. A Fresnel lens (40) is disposed proximate to the substrate for directing the output light toward a second lens. The second lens directs the output light to an image sensor for converting light levels to the digital data, forming an image thereby.
    Type: Application
    Filed: November 22, 2005
    Publication date: May 24, 2007
    Inventors: Victor Wong, Rongguang Liang
  • Publication number: 20070099148
    Abstract: A method for obtaining an image of tooth tissue directs incident light toward a tooth (20), wherein the incident light excites a fluorescent emission from the tooth tissue. Fluorescence image data (50) is obtained from the fluorescent emission. Back-scattered reflectance image data (52) is obtained from back-scattered light from the tooth tissue. The fluorescence and back-scattered reflectance image data are combined to form an enhanced image (64) of the tooth tissue for caries detection.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 3, 2007
    Inventors: Victor Wong, Rongguang Liang, Donna Rankin-Parobek
  • Publication number: 20060245231
    Abstract: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.
    Type: Application
    Filed: June 29, 2006
    Publication date: November 2, 2006
    Inventors: J. Thompson, Jeffrey Wright, Victor Wong, Jim Cullum
  • Publication number: 20060221671
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The out/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Application
    Filed: June 6, 2006
    Publication date: October 5, 2006
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey Wright
  • Patent number: 7082064
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: July 25, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey P. Wright
  • Publication number: 20060148089
    Abstract: The present invention is directed to an apparatus and method for obtaining kinetic information for commercial-form catalysts using minimal catalyst material while approximating large-scale reactor hydrodynamics and heat and mass transfer.
    Type: Application
    Filed: December 28, 2005
    Publication date: July 6, 2006
    Inventors: Nallakkan Arvindan, H. Bergh, Valery Sokolovskii, Victor Wong
  • Publication number: 20060047775
    Abstract: Methods and apparatus for managing download of content to a client device are disclosed. In one aspect, the download process is optimized for bandwidth usage by using criteria such as time of day, level of network activity and priority of download. In another aspect, download of content is prioritized based on certain rules, user inputs and pre-emptive events on the client device. A computer program embodying these methods and a multimedia client device adapted to run this program are also disclosed.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 2, 2006
    Inventors: Timo Bruck, Victor Wong, Thomas Hammer
  • Publication number: 20060013056
    Abstract: A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 19, 2006
    Inventors: J. Thompson, Jeffrey Wright, Victor Wong, Jim Cullum
  • Publication number: 20050274104
    Abstract: Pollution control apparatus. An exhaust aftertreatment unit is fitted to the exhaust of an internal combustion engine and a fuel reformer provides hydrogen rich gas in an optimal way to the aftertreatment unit to regenerate the aftertreatment unit. It is preferred that the hydrogen rich gas be provided only to a portion of the aftertreatment unit at any time to regenerate that portion. Stored hydrogen may be used.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 15, 2005
    Inventors: Leslie Bromberg, Daniel Cohn, Kamal Hadidi, John Heywood, Alexander Rabinovich, Victor Wong
  • Publication number: 20050270058
    Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.
    Type: Application
    Filed: August 9, 2005
    Publication date: December 8, 2005
    Inventors: Joseph Sher, David Siek, Huy Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
  • Publication number: 20050243161
    Abstract: A contact printing apparatus (100), using a direct-coupled emissive array (20) of individual light emitting pixels (22), forms an image from digital data onto a photosensitive medium (16). The direct-coupled emissive array (20) is fabricated on an optically coupled substrate (25) that provides light-directing elements, such as a lenslet array or fiber optic faceplate (40) for directing light from emitter pixels (22) to print pixel (71) locations on the photosensitive medium (16).
    Type: Application
    Filed: May 3, 2004
    Publication date: November 3, 2005
    Inventors: Victor Wong, Badhri Narayan, Gareth Evans
  • Publication number: 20050181940
    Abstract: The present invention addresses at least four different aspects relating to catalyst structure, methods of making those catalysts and methods of using those catalysts for making alkenyl alkanoates. Separately or together in combination, the various aspects of the invention are directed at improving the production of alkenyl alkanoates and VA in particular, including reduction of by-products and improved production efficiency. A first aspect of the present invention pertains to a unique palladium/gold catalyst or pre-catalyst (optionally calcined) that includes rhodium or another metal. A second aspect pertains to a palladium/gold catalyst or pre-catalyst that is based on a layered support material where one layer of the support material is substantially free of catalytic components. A third aspect pertains to a palladium/gold catalyst or pre-catalyst on a zirconia containing support material.
    Type: Application
    Filed: November 19, 2004
    Publication date: August 18, 2005
    Inventors: Tao Wang, Les Wade, Ioan Nicolau, Barbara Kimmich, Victor Wong, Yumin Liu, Jun Han, Valery Sokolovskii, Alfred Hagemeyer, David Lowe
  • Patent number: 6930503
    Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: August 16, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
  • Publication number: 20050169068
    Abstract: A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.
    Type: Application
    Filed: January 29, 2004
    Publication date: August 4, 2005
    Inventors: Mehul Nagrani, Victor Wong, Jeffrey Wright
  • Publication number: 20050018038
    Abstract: An apparatus for printing images from digital image data onto a light sensitive medium disposed at an image plane which comprises a control logic processor capable of controlling the operation of the apparatus for printing based on the digital image data. An image forming assembly directs an exposure beam to the light sensitive medium disposed at the image plane. The image forming assembly (10) comprises a light source, a first lens assembly (41), a beamsplitter (50), a spatial light modulator (52), a temperature profile control apparatus (51) and a second lens assembly (132).
    Type: Application
    Filed: July 22, 2003
    Publication date: January 27, 2005
    Inventors: Sujatha Ramanujan, Julie Gerstenberger, Victor Wong
  • Publication number: 20040206226
    Abstract: An electronic musical performance instrument that provides a user with a wide array of creative choices of operating systems, sound synthesis applications, user interfaces (including those emulating the interface of a conventional musical instrument and electronic control interfaces), supporting infrastructure components such as MIDI cards, sound cards, storage devices thus providing the performance artist with greater and deeper creative flexibility.
    Type: Application
    Filed: January 15, 2004
    Publication date: October 21, 2004
    Inventors: Craig Negoescu, Lary Cotten, Victor Wong
  • Publication number: 20040201399
    Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.
    Type: Application
    Filed: April 30, 2004
    Publication date: October 14, 2004
    Applicant: Micron Technology, Inc.
    Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng
  • Patent number: 6756805
    Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: June 29, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Joseph C. Sher, David D. Siek, Huy Thanh Vo, Nicholas Van Heel, Victor Wong, Hua Zheng