Abstract: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Abstract: The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.

Abstract: The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device.

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.

Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.

Abstract: The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

Abstract: The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device.

Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.

Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.

Abstract: The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.

Abstract: The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device.

Abstract: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Abstract: The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.

Abstract: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Abstract: The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.