Patents by Inventor Victor Ying

Victor Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for processing subtitles
    Patent number: 9800801
    Abstract: Various embodiments are generally directed an apparatus and method for determining a size of a subtitle area in a subtitle image comprising subtitle information, creating a new subtitle image comprising the subtitle information, the new subtitle image having a same size as the size of the subtitle area and is smaller than the subtitle image and combining the new subtitle image with a video image for presenting the subtitle information.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: October 24, 2017
    Assignee: INTEL CORPORATION
    Inventors: Zhiwei Victor Ying, Changliang Charlie Wang
  • TECHNIQUES FOR PROCESSING SUBTITLES
    Publication number: 20160286140
    Abstract: Various embodiments are generally directed an apparatus and method for determining a size of a subtitle area in a subtitle image comprising subtitle information, creating a new subtitle image comprising the subtitle information, the new subtitle image having a same size as the size of the subtitle area and is smaller than the subtitle image and combining the new subtitle image with a video image for presenting the subtitle information.
    Type: Application
    Filed: December 17, 2013
    Publication date: September 29, 2016
    Inventors: ZHIWEI VICTOR YING, CHANGLIANG CHARLIE WANG
  • Mechanism to store reordered data with compression
    Patent number: 7162583
    Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller, coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache controller reorders a cache line after each access to the cache line prior to the compression of the cache line into a compressed cache line.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventors: Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Guei-Yuan Lueh, Victor Ying
  • Mechanism to store reordered data with compression
    Publication number: 20050144386
    Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU), a cache memory coupled to the CPU and a cache controller, coupled to the cache memory. The cache memory includes a plurality of compressible cache lines to store additional data. The cache controller reorders a cache line after each access to the cache line prior to the compression of the cache line into a compressed cache line.
    Type: Application
    Filed: December 29, 2003
    Publication date: June 30, 2005
    Inventors: Ali-Reza Adl-Tabatabai, Anwar Ghuloum, Guei-Yuan Lueh, Victor Ying