Abstract: An apparatus and method for conducting fault sensitivity analysis of a digitally calibrated circuit design includes simulating calibration of the circuit design, simulating calibration of the circuit design with a fault in the analog portion of the circuit design, simulating the circuit design with the fault for a fault interval time period, and determining whether the fault is detectable.

Abstract: In a system, method, and computer program product for analyzing faults in a circuit design, variation of analog fault coverage as a function of bridge resistance values is computed in a single simulation run. A simulator stores intermediate circuit states for each fault resistance value, and performs short interval simulations that may re-use intermediate states as initial solution estimates for simulation of the next fault resistance value. Initial fault resistance values are reduced during simulation passes to aid simulator convergence. The selected evaluation order of test points, faults, and fault resistance values reduces computational and storage costs. Embodiments enable test engineers to rapidly understand if analog defect tests are only sufficient for identifying defects of a certain type and/or value, and to determine fault coverage variability over a full process space.