Abstract: A system and method of data mining for republishing is described. In some embodiments products having a high potential for increased sales through republishing are identified based on relationships with products having consistent sales. In some embodiments products having a high potential for increased sales through republishing are identified based on sales in one language and availability of rights in another language. In one aspect, translations are facilitated via a translations marketplace.

Abstract: This disclosure describes a platform for better connecting authors and retailers that offer works of the authors for acquisition by a community of users. This platform includes multiple tools that allow the authors to provide content to the community of users through the retailer or through another entity. In addition, this platform provides tools that authors may utilize for marketing their works, for tracking acquisition (e.g., sales) of their works, for connecting with other authors, or for a multitude of other purposes.

Abstract: A media access control processor includes a receiver co-processor and a transmitter co-processor. Each co-processor includes its own micro-controller. Depending upon the desired communication protocol being implemented, a programmable logic device controls the loading of an appropriate set of micro-instructions into the micro-controller's memory.

Abstract: A media access control processor includes a receiver co-processor and a transmitter co-processor. Each co-processor includes its own micro-controller. Depending upon the desired communication protocol being implemented, a programmable logic device controls the loading of an appropriate set of micro-instructions into the micro-controller's memory.

Abstract: A data processor and storage system which comprises a data processor, a cache memory and a main memory is arranged so that the addressing of the main memory produces a multiplicity of spaced aliases, the multiplicity being greater than the set-associativity of the cache memory. The cache memory may be a multiple way set associative cache memory with the system including a round robin allocator for controlling the storing of successive data items in the different ways of the set associative cache. The cache may also be a direct mapped cache having single way set-associativity so that the round robin allocator is not required. The system may also include a direct memory access (DMA) device for copying data items into the memory. The memory may be a buffer memory which is divided into a plurality of packet buffers.

Abstract: A data processor and storage system which comprises a data processor, a cache memory and a main memory is arranged so that the addressing of the main memory produces a multiplicity of spaced aliases, the multiplicity being greater than the set-associativity of the cache memory