Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including: a first signal path including a first sample and hold circuit responsive to an input signal for sampling the input signal at a first resolution; a second signal path arranged parallel to the first signal path and including a second sample and hold circuit responsive to the input signal for sampling the input signal at a second resolution; and a control circuit arranged in series with the first and second signal paths and configured to isolate one of the first and second signal paths from an output of the control circuit in response to a control signal.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage having a first signal path including a first sample and hold circuit for sampling an input signal at a first resolution, and a second signal path responsive to the input signal and arranged in parallel with the first signal path. The second signal path includes a second sample and hold circuit for sampling the input signal at a second resolution. A first ADC is also included for generating a digital representation of the input signal sampled by the first converter stage. A control processor is arranged between outputs of the first and second sample and hold circuits and the input of the ADC for selectively providing the signal sampled by one of the first or second sample and hold circuit to the input of the ADC.

Abstract: A clocking scheme for a reconfigurable wideband analog-to-digital converter (ADC) including a plurality of Delay Locked Loops (DLLs) arranged in parallel. Each DLL is responsive to an input clock signal and configured to selectively generate a plurality of output clock signals for controlling the operation of the ADC.