Abstract: A magneto resistive memory device including a memory array with at least one bit line (BL) and at least one source line (SL, SLB), the bit line (BL) and the at least one source line (SL, SLB) associated with a plurality of memory cells each presenting a magnetic tunnel junction and each presenting at least one selection transistor (RT) to selectively connect the bit line (BL). The memory array also includes a peripheral block configured to apply a first voltage (Vread) greater than ground voltage (Vss) on the bit line (BL) and applying a second voltage (VSL) greater than the first voltage (Vread) on the at least one source line (SL, SLB). The state stored in the selected cell is detected by using a sense amplifier (SA) of the peripheral block associated with the at least one bit line (BL) to sense the current flowing in the bit line (BL).

Abstract: A magneto resistive memory device including a memory array with at least one bit line (BL) and at least one source line (SL, SLB), the bit line (BL) and the at least one source line (SL, SLB) associated with a plurality of memory cells each presenting a magnetic tunnel junction and each presenting at least one selection transistor (RT) to selectively connect the bit line (BL). The memory array also includes a peripheral block configured to apply a first voltage (Vread) greater than ground voltage (Vss) on the bit line (BL) and applying a second voltage (VSL) greater than the first voltage (Vread) on the at least one source line (SL, SLB). The state stored in the selected cell is detected by using a sense amplifier (SA) of the peripheral block associated with the at least one bit line (BL) to sense the current flowing in the bit line (BL).

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.

Abstract: One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.

Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.

Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.

Abstract: One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.