Abstract: Insulated gate field effect transistors (10, 70) having process steps for setting the V.sub.T and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the V.sub.T and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the V.sub.T and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.

Abstract: A complementary insulated gate field effect transistor (10) having a partial channel. A gate electrode structure (29, 31) is formed on a dopant well (13, 14). An implant block mask (33, 38) is formed on a portion of the gate structure. An impurity material is implanted into the dopant well to form a dopant region (34, 39) having a first portion (36, 42) and a second portion (37, 41). The implant is of sufficient energy that a portion of the impurity material penetrates a portion gate electrode structure (29, 31) to form the second portion (37, 41) which serves as the partial channel. The partial channel provides the complementary insulated gate field effect transistor (10) with a low subthreshold swing, and improved saturation current and source/drain parasitic capacitance.