Abstract: Various antennas elements including antennas arrays can support various communication technologies and can be integrated into different components or subcomponents of a vehicle, including various vehicle light assemblies. The vehicular antennas elements include low profile and/or concealed antenna elements that are inconspicuous aesthetically and do not affect or substantially affect vehicle aerodynamics.

Abstract: Embodiments of the invention generally provide a method and apparatus for enabling digital rights management in file transfers. One embodiment of a method for transferring digital content from a first user to a second user, includes transferring ownership of an instance of the digital content to the second user, where the instance of the digital content resides on a first device belonging to the first user. Copies of the digital content are then deleted from one or more additional devices belonging to the first user (including at least one offline device).

Abstract: Embodiments of the invention generally provide a method and apparatus for enabling digital rights management in file transfers. One embodiment of a method for transferring digital content from a first user to a second user, includes transferring ownership of an instance of the digital content to the second user, where the instance of the digital content resides on a first device belonging to the first user. Copies of the digital content are then deleted from one or more additional devices belonging to the first user (including at least one offline device).

Abstract: Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 ?, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.

Abstract: Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 ?, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.

Abstract: A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP also includes a base region of a second conductivity type formed by a graded channel implant and a well region of a second conductivity type, the well region contacting the base region, the buried region and a base contact. Additionally, there are collector contacts and emitter contacts of a first conductivity type. The lightly doped collector region results in a large Early voltage and the base region provides for a high current gain.

Abstract: A method of manufacturing a heterojunction BiCMOS IC. (100) includes forming a gate electrode (121, 131), forming a protective layer (901, 902) over the gate electrode, forming a semiconductor layer (1101) over the protective layer, depositing an electrically insulative layer (1102, 1103) over the semiconductor layer, using a mask layer (1104) to define a doped region (225) in the semiconductor layer and to define a hole (1201) in the electrically insulative layer, forming an electrically conductive layer (1301) over the electrically insulative layer, using another mask layer (1302) to define an emitter region (240) in the electrically conductive layer and to define an intrinsic base region (231) and a portion of an extrinsic base region (232) in the electrically conductive layer, and using yet another mask layer (1502) to define another portion of the extrinsic base region in the electrically conductive layer.

Abstract: An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

Abstract: A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adjacent to source region (41) such that after subsequent thermal processing, a constant doping profile of opposite conductivity as source region (41) is formed in the channel region (23) adjacent the source region (41). The embodiments can be formed either adjacent to only the source region (41) to create a unilateral device, or the doping profile can be formed adjacent to both source region (41) and a drain region (40) to produce a bilateral device. An additional embodiment forms a second implant region in source region (41) to reduce junction leakage and capacitance.

Abstract: An insulated gate semiconductor device (10) having a gate structure (45) that includes a conductive spacer (32) and an extension region (46) extending from the conductive spacer (32). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate dielectric (23) is then formed over the major surface (12) adjacent to the sidewalls (22). The conductive spacer (32) is formed on the gate dielectric (23). The extension region (46) is then formed using selective growth or deposition and patterning of polysilicon adjacent the conductive spacer (32).

Abstract: An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

Abstract: Portions of a semiconductor device (10,30) are formed from a dielectric layer (16,38,46) which is deposited using a plasma enhanced chemical vapor deposition (PECVD) process which adds trimethylphosphite as a dopant source during the deposition. A first embodiment forms sidewall spacers (17) adjacent to a gate structure (14) and forms doped regions (19) under the sidewall spacers (17) by annealing the dielectric layer (16) and driving phosphorus into a substrate (11). A second embodiment uses the trimethylphosphite doped film as an interlevel dielectric layer (38) which can be planarized to provide a flat surface for the formation of metal interconnect lines. A third embodiment of the present invention uses the trimethylphosphite doped film as a passivation layer (46) which is deposited in a single step process and has a phosphorus concentration to getter mobile ions.

Abstract: An insulated gate field effect transistor (IGFET) structure (10) includes a source region (14) and a drain region (16) formed in an impurity well (13). A channel region (18) separates the source region (14) from the drain region (16). In one embodiment, a unilateral extension region (17) is formed adjacent the source region (14) only and extends into the channel region (18). The unilateral extension region (17) has a peak dopant concentration at a depth (23) and a lateral distance (24) to provide punchthrough resistance. The IGFET structure (10) is suitable for low (i.e., 0.2-0.3 volts) to medium (0.5-0.6 volts) threshold voltage reduced channel length applications.

Abstract: A method for forming a unilateral, graded-channel field effect transistor and a transistor stock 200 that includes providing a substrate (10) with an overlying gate electrode (14, 16). A spacer (23) is formed on only the drain side of the electrode. A graded-channel region (36) is formed aligned to the source side of the electrode while the spacer protects the drain side of the channel region. Source/drain regions (38) are formed, the spacer is removed, and then a drain extension region (40) is formed aligned to the drain side of the electrode.

Abstract: An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.

Abstract: A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adjacent to source region (41) such that after subsequent thermal processing, a constant doping profile of opposite conductivity as source region (41) is formed in the channel region (23) adjacent the source region (41). The embodiments can be formed either adjacent to only the source region (41) to create a unilateral device, or the doping profile can be formed adjacent to both source region (41) and a drain region (40) to produce a bilateral device. An additional embodiment forms a second implant region in source region (41) to reduce junction leakage and capacitance.

Abstract: A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Abstract: An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.

Abstract: An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

Abstract: A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits higher packing density, and lowers buried layer-to-substrate capacitance.