Patents by Inventor Vidhumouli Hunsigida

Vidhumouli Hunsigida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10891414
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele
  • Publication number: 20200371759
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Akella Sastry, Vinod K. Kathail, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddarth Rele
  • Publication number: 20200372123
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele