Patents by Inventor VIDHYA CHAKRAPANI

VIDHYA CHAKRAPANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12389712
    Abstract: A solar cell device having a solid state light absorber region that incorporates a donor-acceptor particle structure. The particle structure includes acceptor particles that generate a flow of electrons in the solid state light absorber region in response to absorbed photons; and donor particles comprising a phosphorescent material, wherein each donor particle is coupled to a group of acceptor particles, and wherein the phosphorescent material absorbs high energy photons and emits lower energy photons that are absorbed by the acceptor particles.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: August 12, 2025
    Assignee: Rensselaer Polytechnic Institute
    Inventor: Vidhya Chakrapani
  • Publication number: 20230335662
    Abstract: A solar cell device having a solid state light absorber region that incorporates a donor-acceptor particle structure. The particle structure includes acceptor particles that generate a flow of electrons in the solid state light absorber region in response to absorbed photons; and donor particles comprising a phosphorescent material, wherein each donor particle is coupled to a group of acceptor particles, and wherein the phosphorescent material absorbs high energy photons and emits lower energy photons that are absorbed by the acceptor particles.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 19, 2023
    Applicant: Rensselaer Polytechnic Institute
    Inventor: Vidhya Chakrapani
  • Patent number: 11682743
    Abstract: A solar cell device having a solid state light absorber region that incorporates a donor-acceptor particle structure. The particle structure includes acceptor particles that generate a flow of electrons in the solid state light absorber region in response to absorbed photons; and donor particles comprising a phosphorescent material, wherein each donor particle is coupled to a group of acceptor particles, and wherein the phosphorescent material absorbs high energy photons and emits lower energy photons that are absorbed by the acceptor particles.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: June 20, 2023
    Assignee: Rensselaer Polytechnic Institute
    Inventor: Vidhya Chakrapani
  • Publication number: 20220077341
    Abstract: A solar cell device having a solid state light absorber region that incorporates a donor-acceptor particle structure. The particle structure includes acceptor particles that generate a flow of electrons in the solid state light absorber region in response to absorbed photons; and donor particles comprising a phosphorescent material, wherein each donor particle is coupled to a group of acceptor particles, and wherein the phosphorescent material absorbs high energy photons and emits lower energy photons that are absorbed by the acceptor particles.
    Type: Application
    Filed: November 15, 2021
    Publication date: March 10, 2022
    Applicant: Rensselaer Polytechnic Institute
    Inventor: Vidhya Chakrapani
  • Publication number: 20180025849
    Abstract: A solar cell device having a solid state light absorber region that incorporates a donor-acceptor particle structure. The particle structure includes acceptor particles that generate a flow of electrons in the solid state light absorber region in response to absorbed photons; and donor particles comprising a phosphorescent material, wherein each donor particle is coupled to a group of acceptor particles, and wherein the phosphorescent material absorbs high energy photons and emits lower energy photons that are absorbed by the acceptor particles.
    Type: Application
    Filed: February 11, 2016
    Publication date: January 25, 2018
    Inventor: Vidhya Chakrapani
  • Patent number: 9153457
    Abstract: A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: October 6, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Vidhya Chakrapani, Akiteru Ko, Kaushik A. Kumar
  • Patent number: 8945408
    Abstract: Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the surface of the substrate, the etching process being performed at a substrate temperature less than or equal to about 20 degrees C. The method further comprises providing a substrate holder for supporting the substrate, the substrate holder having a first temperature control element for controlling a first temperature at a central region and second temperature control element at an edge region of the substrate and setting a target value for the first and the second temperature.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 3, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Vidhya Chakrapani, Akiteru Ko, Kaushik Kumar
  • Publication number: 20140370717
    Abstract: Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the surface of the substrate, the etching process being performed at a substrate temperature less than or equal to about 20 degrees C. The method further comprises providing a substrate holder for supporting the substrate, the substrate holder having a first temperature control element for controlling a first temperature at a central region and second temperature control element at an edge region of the substrate and setting a target value for the first and the second temperature.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: VIDHYA CHAKRAPANI, AKITERU KO, KAUSHIK KUMAR
  • Publication number: 20140370718
    Abstract: A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed.
    Type: Application
    Filed: September 4, 2013
    Publication date: December 18, 2014
    Applicant: Tokyo Electron Limited
    Inventors: VIDHYA CHAKRAPANI, AKITERU KO, KAUSHIK KUMAR