Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry will sort received memory access messages into address sorted lists of reads and writes. The circuitry schedules a first set of address sorted requests from a first request buffer for a first period of time, then schedules a second set of address sorted requests from a second request buffer for a second period of time.

Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.

Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

Abstract: Described herein is a paging technique that can be implemented in any accelerator with attached memory and support for operating on encrypted data when the CPU is not within the trusted compute base (TCB). Memory storing data that is encrypted using hardware physical address (HPA)-based encrypted can be paged out of accelerator device memory by decoupling encryption from the hardware physical address and re-encrypting the data for page-out. Upon page-in, the data is decrypted, the integrity and authenticity of the data is verified, then the data is re-encrypted using HPA-based encryption.

Abstract: Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.

Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

Abstract: One embodiment provides an apparatus comprising a graphics processor device including a first compute engine and a second compute engine, wherein the second compute engine includes a subset of the functionality provided by the first compute engine and a lower power consumption relative to the first compute engine.

Abstract: Dynamic integrity verification of shaders for processing of workloads is described. An example of an apparatus includes one or more processors including a GPU, the GPU including circuitry for dynamic verification of shaders; and a memory for storage of data, including data for one or more workloads of the GPU, the one or more processors to identify one or more shaders that can operate on protected content in the one or more workloads; transfer binary blocks of the one or more shaders to a trusted execution environment of the GPU to authenticate the one or more shaders; load hashes for the binary blocks of the one or more shaders into memory; and send a hardware command that points to a first shader of the one or more shaders for dynamic verification of the first shader.

Abstract: Systems, computer program products, and methods are described for secure data transmission. An example system includes a first end-point device, an intermediate device, and a second-end point device. The first end-point device determines the format requirements of the communication link between the first end-point device and the intermediate device, and the communication link intermediate device and the second end-point device. Based on the format requirements, the first end-point device configures the data packet for transmission, such that the data packet, when received at the intermediate device, is re-configured and routed to the second end-point device. When the second end-point device receives the data packet, it verifies the data packet to confirm that the packet has maintained its integrity throughout transit.

Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

Abstract: Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.

Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.

Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

Abstract: Described herein is a paging technique that can be implemented in any accelerator with attached memory and support for operating on encrypted data when the CPU is not within the trusted compute base (TCB). Memory storing data that is encrypted using hardware physical address (HPA)-based encrypted can be paged out of accelerator device memory by decoupling encryption from the hardware physical address and re-encrypting the data for page-out. Upon page-in, the data is decrypted, the integrity and authenticity of the data is verified, then the data is re-encrypted using HPA-based encryption.

Abstract: A lossless pixel compressor may include technology to detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region. Other embodiments are disclosed and claimed.

Abstract: A graphics processor includes multiple levels of memory units, including a memory device and a cache device located near a graphics component. The graphics processor includes distributed compression/decompression, including a module between the cache device and the memory device. The module can perform compression of write data when the write data is moved from the cache device to the memory device, and perform decompression of read data when the read data is moved from the memory device to the cache device. The graphics processor can include a second level of cache with another compression module between the first level of cache and the second level of cache.

Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.

Abstract: One embodiment provides an apparatus comprising a graphics processor device including a first compute engine and a second compute engine, wherein the second compute engine includes a subset of the functionality provided by the first compute engine and a lower power consumption relative to the first compute engine.