Patents by Inventor VIDHYA KRISHNAN
VIDHYA KRISHNAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11816040Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.Type: GrantFiled: April 2, 2022Date of Patent: November 14, 2023Assignee: INTEL CORPORATIONInventors: Vidhya Krishnan, Siddhartha Chhabra, David Puffer, Ankur Shah, Daniel Nemiroff, Utkarsh Y. Kakaiya
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Publication number: 20230306551Abstract: Described herein is a graphics processor comprising a processing resource configured to perform processing operations, a codec configured to compress and decompress data associated with the processing operations, and circuitry configured to calculate a metadata address for a compressed surface based on a flat virtual memory address mapping between the address of the compressed surface and the metadata address. The compressed surface is to store data associated with a processing operation to be performed by the processing resource and the metadata address is a virtual address that stores compression metadata for the compressed surface. The circuitry can configure the codec to access the compressed surface based on the compression metadata.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Applicant: Intel CorporationInventors: Vidhya Krishnan, Niranjan Cooray, David Puffer, Ronald Silvas, Durgaprasad Bilagi, Aditya Navale
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Publication number: 20230297421Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Cowperthwaite, Kenneth Daxer, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Hema Chand Nalluri, Jeffery S. Boles, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala, Michael Apodaca
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Publication number: 20230297440Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Cowperthwaite, Kenneth Daxer, Jeffery S. Boles, Hema Chand Nalluri, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala
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Publication number: 20230298125Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Hema Chand Nalluri, Jeffery S. Boles, David Cowperthwaite, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Ankur Shah, Vidhya Krishnan, Kritika Bala, Aravindh Anantaraman, Michael Apodaca, Kenneth Daxer
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Publication number: 20230291567Abstract: Described herein is a paging technique that can be implemented in any accelerator with attached memory and support for operating on encrypted data when the CPU is not within the trusted compute base (TCB). Memory storing data that is encrypted using hardware physical address (HPA)-based encrypted can be paged out of accelerator device memory by decoupling encryption from the hardware physical address and re-encrypting the data for page-out. Upon page-in, the data is decrypted, the integrity and authenticity of the data is verified, then the data is re-encrypted using HPA-based encryption.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Applicant: Intel CorporationInventors: VIDHYA KRISHNAN, SIDDHARTHA CHHABRA, VEDVYAS SHANBHOGUE, XIAOYU RUAN, ADITYA NAVALE, JULIEN CARRENO
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Patent number: 11729403Abstract: A lossless pixel compressor may include technology to detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region. Other embodiments are disclosed and claimed.Type: GrantFiled: December 5, 2017Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: James Holland, Hiu-Fai Chan, Fangwen Fu, Qian Xu, Sang-Hee Lee, Vidhya Krishnan
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Publication number: 20230206383Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Karol A. SZERSZEN, Prasoonkumar SURTI, Vidhya KRISHNAN, Aditya NAVALE, Abhishek R. APPU, Altug KOKER, Ronald W. SILVAS
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Publication number: 20230205704Abstract: A graphics processor includes multiple levels of memory units, including a memory device and a cache device located near a graphics component. The graphics processor includes distributed compression/decompression, including a module between the cache device and the memory device. The module can perform compression of write data when the write data is moved from the cache device to the memory device, and perform decompression of read data when the read data is moved from the memory device to the cache device. The graphics processor can include a second level of cache with another compression module between the first level of cache and the second level of cache.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Prasoonkumar SURTI, Vidhya KRISHNAN, Abhishek R. APPU, Karol A. SZERSZEN, Lakshminarayanan STRIRAMASSARMA
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Publication number: 20230195519Abstract: One embodiment provides an apparatus comprising a graphics processor device including a first compute engine and a second compute engine, wherein the second compute engine includes a subset of the functionality provided by the first compute engine and a lower power consumption relative to the first compute engine.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Vidhya Krishnan, Chien-Wei Li, Ben J. Ashbaugh, Durgaprasad Bilagi, Pattabhiraman K
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Publication number: 20230104845Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry will sort received memory access messages into address sorted lists of reads and writes. The circuitry schedules a first set of address sorted requests from a first request buffer for a first period of time, then schedules a second set of address sorted requests from a second request buffer for a second period of time.Type: ApplicationFiled: September 24, 2021Publication date: April 6, 2023Applicant: Intel CorporationInventors: Joydeep Ray, Abhishek R. Appu, Altug Koker, Aditya Navale, Varghese George, Vasanth Ranganathan, Fangwen Fu, Ben J. Ashbaugh, Vidhya Krishnan, Sabareesh Ganapathy, Prathamesh Raghunath Shinde
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Publication number: 20230094002Abstract: Dynamic routing of texture-load in graphics processing is described. An example of an apparatus includes a graphics processor including a plurality of processing engines of a class of processing engines of the graphic processor; a set of queues for the plurality of processing engines; and a unified submit port for the plurality of processing engines, wherein the unified submit port is to notify a scheduler regarding availability of slots in the set of queues for receipt of workload contexts; and wherein, upon the unified submit port receiving a workload context for processing by the plurality of processing engines, the unified submit port is to detect an available processing engine of the plurality of processing engines and direct the received context to a slot of the set of queues for processing by the available processing engine.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Hema Chand Nalluri, Jeffery S. Boles, Joseph Koston, Ankur N. Shah, Vidhya Krishnan, Vasanth Ranganathan, Joydeep Ray, Aditya Navale, Murali Ramadoss, James Valerio
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Patent number: 11416402Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.Type: GrantFiled: October 12, 2020Date of Patent: August 16, 2022Assignee: INTEL CORPORATIONInventors: Niranjan L. Cooray, Altug Koker, Vidhya Krishnan, Ronald W. Silvas, John H. Feit, Prasoonkumar Surti, Joydeep Ray, Abhishek R. Appu
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Publication number: 20220222185Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.Type: ApplicationFiled: April 2, 2022Publication date: July 14, 2022Applicant: Intel CorporationInventors: Vidhya Krishnan, Siddhartha Chhabra, David Puffer, Ankur Shah, Daniel Nemiroff, Utkarsh Y. Kakaiya
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Publication number: 20220222340Abstract: Security and support for trust domain operation is described. An example of a method includes processing, at an accelerator, one or more compute workloads received from a host system; upon receiving a notification that a trust domain has transitioned to a secure state, transition an original set of privileges for the accelerator to a downgraded set of privileges; upon receiving a command from the host system for the trust domain, processing the command in accordance with the trust domain; and upon receiving a request from the host system to access a register, for a register included in an allowed list of registers for access, allow access to the register, and, for a register that is not within the allowed list of registers for access, disallowing access to the register.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Applicant: Intel CorporationInventors: Vidhya Krishnan, Ankur Shah, Bryan White, Daniel Nemiroff, David Puffer, Julien Carreno, Scott Janus, Ravi Sahita, Hema Nalluri, Utkarsh Y. Kakaiya
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Publication number: 20220138286Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.Type: ApplicationFiled: December 23, 2020Publication date: May 5, 2022Applicant: Intel CorporationInventors: David Zage, Scott Janus, Ned M. Smith, Vidhya Krishnan, Siddhartha Chhabra, Rajesh Poornachandran, Tomer Levy, Julien Carreno, Ankur Shah, Ronald Silvas, Aravindh Anantaraman, David Puffer, Vedvyas Shanbhogue, David Cowperthwaite, Aditya Navale, Omer Ben-Shalom, Alex Nayshtut, Xiaoyu Ruan
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Publication number: 20220004635Abstract: An apparatus is disclosed. The apparatus comprises a trusted device including a first integrated circuit (IC) die comprising a first plurality of hardware devices and a second IC die comprising a second plurality of hardware devices and cryptographic processor to operate as a root of trust to manage an input/output (I/O) functional state of each of the hardware devices.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Applicant: Intel CorporationInventors: Daniel Nemiroff, Vidhya Krishnan, Bryan R. White
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Patent number: 11018863Abstract: An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.Type: GrantFiled: June 7, 2019Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Balaji Vembu, Vidhya Krishnan, Sandeep S. Sodhi, Scott Janus, Daniel Nemiroff
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Patent number: 10969999Abstract: An apparatus to facilitate a tracking of surface properties is disclosed. The apparatus includes one or more processors to receive a memory request, access a virtual to virtual page table to retrieve an address storing surface properties metadata, and process the memory request, wherein the virtual to virtual page table provides a mapping between a main surface and an auxiliary surface including the surface properties metadata.Type: GrantFiled: December 28, 2018Date of Patent: April 6, 2021Assignee: Intel CorporationInventors: Vidhya Krishnan, Niranjan Cooray, Prasoonkumar Surti, John Feit
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Publication number: 20210049098Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.Type: ApplicationFiled: October 12, 2020Publication date: February 18, 2021Applicant: Intel CorporationInventors: NIRANJAN L. COORAY, Altug Koker, Vidhya Krishnan, Ronald W. Silvas, John H. Feit, Prasoonkumar Surti, Joydeep Ray, Abhishek R. Appu