Abstract: Methods, apparatus, systems, and articles of manufacture to process web-scale graphs are disclosed. An example apparatus comprises: at least one memory; instructions; and processor circuitry to execute the instructions to: retrieve a compute based tile (CBT) from a first external memory, the CBT to include source and destination nodes of a graph; assign a stripe of the CBT to a single instruction multiple data compute unit, the stripe including a first tile and a second tile, the first tile to include first destination nodes and first source nodes, the second tile to include the first destination nodes and second source nodes; retrieve source node embeddings of the stripe based on a node identifier to source node embedding lookup; and provide the source node embeddings to the single instruction multiple data compute unit.

Abstract: Graph reordering and tiling techniques are described herein. In one example, large graphs (e.g., for inferencing with graph neural networks) can be reordered, tiled, or both, to achieve maximal data reuse and uniform compute load distribution. In one example, a reordering method involves performing breadth first search (BFS) renumbering on a graph data set with the highest degree destination node as the root node to generate a reordered graph data set. BFS is then performed again with candidate nodes from the last level of the reordered graph. The second reordered graph data set with the lowest bandwidth or best profile can be selected for further processing. In one example, a method of tiling involves dividing a graph data set into tiles to balance expected compute time.

Abstract: Systems, apparatuses and methods include technology that determines, with a first processing engine of a plurality of processing engines, a first partial similarity measurement based on a first portion of a query vector and a first portion of a first candidate vector. The technology determines, with a second processing engine of the plurality of processing engines, a total similarity measurement based on the query vector and a second candidate vector. The technology determines, with the first processing engine, whether to compare a second portion of the query vector to a second portion of the first candidate vector based on the first partial similarity measurement and the total similarity measurement.

Abstract: Methods and apparatuses that relate to an integrated circuit (IC) with adaptive power state management are described. The IC can be coupled with, and can control the operation of, a memory device. The IC and the memory device can be operated in multiple operational states, wherein each operational state may represent a tradeoff point between performance and power consumption. The IC may be capable of: (1) changing the operational state of the IC and/or the operational state of the memory device based on the occurrence of one or more conditions, and/or (2) changing the one or more conditions based on measuring one or more performance values associated with the IC and/or the memory device.

Abstract: Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory configuration may be stored in mode register bits (228), settable by a host or operating system. By re-configuring or reallocating certain resources of a memory controller, for example command logic blocks (A, B, C, D in FIG. 1A), a single controller design can be used to interface efficiently with a variety of different memory components. Command logic blocks that support N×M memory ranks, for example, can be reconfigured to support N ranks and M threads for multi-threaded memories (FIG. 1A). Data buffer (232, 254) depth can be extended by reconfiguring the buffers responsive to the mode register bits (228). Request buffers can be shared across command logic blocks, for example to increase the request buffer depth (FIG. 3A). Unused circuits can be powered down to save power consumption (FIG. 4A).

Abstract: A multi-channel memory controller (110, 600) may be dynamically re-architected to schedule low and high-latency memory access requests differently (FIG. 12) in order to make more efficient use of memory resources and improve overall performance. Data may be duplicated or “cloned” in a clone area (612) of one or more channels of a multi-channel or module threaded memory (610), the clone area being reserved by the memory controller. Cloning information is stored in a clone mapping table 620, preferably reflecting memory channel locations, including clone locations, per memory address range. An operating system may request a selected number of channels for cloning, see (622), based on application latency requirements or sensitivity, by storing the request in the clone mapping table. Coarse granularity access requests also may be dynamically scheduled across one or more first-available channels of the multi-channel or module threaded memory (1504) in a modified controller (1500).