Patents by Inventor Vidya Kaushik

Vidya Kaushik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7820538
    Abstract: A polycrystalline silicon layer is deposited on a gate dielectric and then a portion thereof is re-oxidized so as to form a thin layer of oxide between the poly-Si layer and the underlying gate dielectric. Subsequently, the poly-Si layer is converted to a fully-silicided form so as to produce a FUSI gate. The gate dielectric can be a high-k material, for example a Hf-containing material, or SION, or another non-SiO2 dielectric. The barrier oxide layer is preferably less than 1 nm thick.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vidya Kaushik
  • Patent number: 7622387
    Abstract: A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: November 24, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vidya Kaushik, Benoit Froment
  • Publication number: 20080197498
    Abstract: A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.
    Type: Application
    Filed: August 29, 2005
    Publication date: August 21, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Vidya Kaushik, Benoit Froment
  • Publication number: 20080194092
    Abstract: A polycrystalline silicon layer is deposited on a gate dielectric and then a portion thereof is re-oxidized so as to form a thin layer of oxide between the poly-Si layer and the underlying gate dielectric. Subsequently, the poly-Si layer is converted to a fully-silicided form so as to produce a FUSI gate. The gate dielectric can be a high-k material, for example a Hf-containing material, or SION, or another non-SiO2 dielectric. The barrier oxide layer is preferably less than 1 nm thick.
    Type: Application
    Filed: April 21, 2005
    Publication date: August 14, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Vidya Kaushik
  • Publication number: 20080135951
    Abstract: It is known to provide a reoxidation step in the manufacture of a MOSFET that serves a number of structural purposes in relation to the MOSFET. However, the need to provide materials of high dielectric constant for gate insulator layers of MOSFETs to accommodate a drive for smaller integrated circuits has led to excessive growth of an SiO2 interfacial layer between the gate insulator layer and a substrate. Excessive growth of the SiO2 layer results in an Effective Oxide Thickness that leads to increased leakage current in the MOSFET. Further, the replacement of polysilicon with metals as electrodes precludes oxygen exposure during processing. Consequently, the present invention provides replacing or preceding the reoxidation step with the deposition of an oxygen barrier layer over at least side walls of a gate electrode of the MOSFET, thereby providing a barrier for oxygen diffusion to the dielectric interface and metal gate electrode that prevents EOT increase and preserves metal gate electrode integrity.
    Type: Application
    Filed: September 21, 2004
    Publication date: June 12, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventor: Vidya Kaushik