Abstract: Disclosed herein are inexpensive, easy-to-install (do-it-yourself/DIY), non-invasive, independently powered automated devices, apparatuses, systems and methods for leak detection, prevention and mitigation, particularly fluid leak detection, prevention and mitigation, as well as water leak detection and water-supply shutoff of domestic and commercial pressurized water-supply networks.

Abstract: An apparatus for training lacrosse technique mechanics includes a lacrosse head which includes a base portion and a housing removably coupled to the base portion. The housing includes a sensor for sensing the motion of the lacrosse head and generating motion data therefrom. The housing also includes a transceiver for transmitting the motion data to an end user device via a network.

Abstract: An apparatus for training lacrosse technique mechanics includes a lacrosse head which includes a base portion and a housing removably coupled to the base portion. The housing includes a sensor for sensing the motion of the lacrosse head and generating motion data therefrom. The housing also includes a transceiver for transmitting the motion data to an end user device via a network.

Abstract: An apparatus for training lacrosse technique mechanics includes a lacrosse head which includes a base portion and a housing removably coupled to the base portion. The housing includes a sensor for sensing the motion of the lacrosse head and generating motion data therefrom. The housing also includes a transceiver for transmitting the motion data to an end user device via a network.

Abstract: A reference signal generator includes an integrated circuit substrate having a semiconductor resonator therein. The resonator includes an inductor extending adjacent a first surface of the integrated circuit substrate. A vertically-stacked composite of at least first and second electrically insulating dielectric layers is provided on the integrated circuit substrate. The vertically-stacked composite covers a portion of the first surface, which extends opposite the inductor. A first electrically conductive shielding layer is provided on a portion of the second electrically insulating dielectric layer extending opposite the inductor. The first electrically conductive shielding layer may encapsulate exposed portions of the first and second electrically insulating dielectric layers. The shielding layer may operate as an electromagnetic shield between the inductor and an external structure, such as an integrated circuit package, and also shield against environmental contamination (e.g.

Abstract: Exemplary embodiments provide a reference signal generator having a reference or center frequency within a predetermined variance over variations in temperature within a specified range. An exemplary apparatus comprises a reference resonator to generate a first reference signal having a resonant frequency, with the reference resonator having a first temperature dependence; and a plurality of switchable circuits, with at least one switchable circuit providing a second temperature dependence opposing the first temperature dependence to maintain the resonant frequency within a predetermined variance over a temperature variation.

Abstract: Exemplary embodiments provide a reference signal generator having a reference or center frequency within a predetermined variance over variations in temperature within a specified range. An exemplary apparatus comprises a reference resonator to generate a first reference signal having a resonant frequency, with the reference resonator having a first temperature dependence; and a plurality of switchable circuits, with at least one switchable circuit providing a second temperature dependence opposing the first temperature dependence to maintain the resonant frequency within a predetermined variance over a temperature variation.

Abstract: There is disclosed an apparatus for designing and optimizing a memory for use in an embedded processing system. The apparatus comprises: 1) a simulation controller for simulating execution of a test program to be executed by the embedded processing system; 2) a memory access monitor for monitoring memory accesses to a simulated memory space during the simulated execution of the test program, wherein the memory access monitor generates memory usage statistical data associated with the monitored memory accesses; and 3) a memory optimization controller for comparing the memory usage statistical data and one or more predetermined design criteria associated with the embedded processing system and, in response to the comparison, determining at least one memory configuration capable of satisfying the one or more predetermined design criteria.

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA.

Abstract: There is disclosed a memory capable of storing a present value and at least one past value of a variable accessible by a first memory address. The memory comprises a memory block comprising R rows of memory cells and a row address decoder for decoding the first memory address. During a read operation, the row address decoder causes data to be retrieved from a row in which data stored to the first memory address was last written. During a write operation, the row address decoder causes data to be stored in a next-sequential row following the last-written row.

Abstract: There is disclosed a field programmable gate array for use in an integrated processing system capable of testing other embedded circuit components in the integrated processing system. The field programmable gate array detects a trigger signal (such as a power reset) in the integrated processing system. In response to the trigger signal, the field programmable gate array receives first test program instructions from a first external source and executes the first test program instructions in order to test the other embedded circuit components in the integrated processing system. When testing of the other embedded circuit components is complete, the field programmable gate array loads its normal operating code and performs its normal functions.

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA.

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA.

Abstract: There is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches.

Abstract: An apparatus for monitoring a load current drawn by an electrical circuit in a wire includes: 1) a Lorentz force MOS transistor having a first drain current (ID1) and a second drain current (ID2), wherein the Lorentz force MOS transistor is disposed proximate the wire carrying the load current and wherein a magnetic force generated by the load current increases a first current difference between the first drain current and a second drain current; 2) a current difference amplification circuit for detecting the first current difference between the first drain current and the second drain current and generating an amplified output signal; and 3) a current monitoring circuit coupled to the current difference amplification circuit capable of detecting and measuring the amplified output signal.

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA.

Abstract: There is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches.

Abstract: There is disclosed a field programmable gate array for use in an integrated processing system capable of testing other embedded circuit components in the integrated processing system. The field programmable gate array detects a trigger signal (such as a power reset) in the integrated processing system. In response to the trigger signal, the field programmable gate array receives first test program instructions from a first external source and executes the first test program instructions in order to test the other embedded circuit components in the integrated processing system. When testing of the other embedded circuit components is complete, the field programmable gate array loads its normal operating code and performs its normal functions.