Patents by Inventor Vidyadhar VUPPULA

Vidyadhar VUPPULA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for an asynchronous successive approximation register analog-to-digital converter with word completion algorithm
    Patent number: 11811419
    Abstract: Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors and compare signals at outputs of the switched capacitors. The SAR ADC may also determine, based on a value of a tunable time interval, whether to set a metastability flag for a first bit to be evaluated and update the value of the tunable time interval based on whether the metastability flag was set.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: November 7, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Oleksiy Zabroda, Vidyadhar Vuppula
  • METHOD AND SYSTEM FOR AN ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH WORD COMPLETION ALGORITHM
    Publication number: 20220182069
    Abstract: Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors and compare signals at outputs of the switched capacitors. The SAR ADC may also determine, based on a value of a tunable time interval, whether to set a metastability flag for a first bit to be evaluated and update the value of the tunable time interval based on whether the metastability flag was set.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Inventors: Oleksiy ZABRODA, Vidyadhar VUPPULA