Patents by Inventor Vidyut Gopal
Vidyut Gopal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130048937Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Applicant: INTERMOLECULAR, INC.Inventors: Jinhong Tong, Randall Higuchi, Imran Hashim, Vidyut Gopal
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Publication number: 20130034947Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.Type: ApplicationFiled: August 5, 2011Publication date: February 7, 2013Applicant: INTERMOLECULAR, INC.Inventors: Zhendong Hong, Hieu Pham, Randall Higuchi, Vidyut Gopal, Imran Hashim
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Patent number: 8288297Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.Type: GrantFiled: September 1, 2011Date of Patent: October 16, 2012Assignee: Intermolecular, Inc.Inventors: Yun Wang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik, Tony Chiag
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Publication number: 20110186117Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. A glass/ceramic handling layer is then formed on the PV cell structures. The PV cell structures with handling layers are then exfoliated from the mother wafer. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels. The glass/ceramic handling layers provide structural integrity to the thin epitaxial solar cells during the separation process and subsequent handling.Type: ApplicationFiled: April 23, 2010Publication date: August 4, 2011Inventors: Ananda H. Kumar, Tirunelveli S. Ravi, Vidyut Gopal
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Patent number: 7972962Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.Type: GrantFiled: September 21, 2010Date of Patent: July 5, 2011Assignees: Spansion LLC, Globalfoundries Inc.Inventors: David Matsumoto, Vidyut Gopal
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Publication number: 20110008966Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.Type: ApplicationFiled: September 21, 2010Publication date: January 13, 2011Applicants: SPANSION LLC, GLOBALFOUNDRIES INC.Inventors: David MATSUMOTO, Vidyut Gopal
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Patent number: 7829464Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.Type: GrantFiled: October 20, 2006Date of Patent: November 9, 2010Assignees: Spansion LLC, GlobalFoundries Inc.Inventors: David Matsumoto, Vidyut Gopal
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Patent number: 7696094Abstract: A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.Type: GrantFiled: December 27, 2006Date of Patent: April 13, 2010Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: David Matsumoto, Michael Brennan, Vidyut Gopal, Jean Yang
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Patent number: 7569500Abstract: Methods of forming metal compounds such as metal oxides or metal nitrides by sequentially introducing and then reacting metal organic compounds with ozone one or with oxygen radicals or nitrogen radicals formed in a remote plasma chamber. The metal compounds have surprisingly and significantly improved uniformity when deposited by atomic layer deposition with cycle times of at least 10 seconds. The metal compounds also do not contain detectable carbon when the metal organic compound is vaporized at process conditions in the absence of solvents or excess ligands.Type: GrantFiled: May 31, 2006Date of Patent: August 4, 2009Assignee: Applied Materials, Inc.Inventors: Craig R. Metzner, Shreyas S. Kher, Vidyut Gopal, Shixue Han, Shankarram A. Athreya
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Patent number: 7569501Abstract: Embodiments of the invention provide methods for forming hafnium materials, such as oxides and nitrides, by sequentially exposing a substrate to hafnium precursors and active oxygen or nitrogen species (e.g., ozone, oxygen radicals, or nitrogen radicals). The deposited hafnium materials have significantly improved uniformity when deposited by these atomic layer deposition (ALD) processes. In one embodiment, an ALD chamber contains an expanding channel having a bottom surface that is sized and shaped to substantially cover a substrate positioned on a substrate pedestal. During an ALD process for forming hafnium materials, process gases form a vortex flow pattern while passing through the expanding channel and sweep across the substrate surface. The substrate is sequentially exposed to chemical precursors that are pulsed into the process chamber having the vortex flow.Type: GrantFiled: May 31, 2006Date of Patent: August 4, 2009Assignee: Applied Materials, Inc.Inventors: Craig R. Metzner, Shreyas S. Kher, Vidyut Gopal, Shixue Han, Shankarram A. Athreya
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Publication number: 20090154215Abstract: Devices and/or methods that facilitate reducing cross-talk noise and/or complementary bit disturb between adjacent storage elements in a memory device are presented. A memory device includes a memory array with wordlines formed in a zig-zag pattern such that each wordline can have segments that are parallel to the x-axis and other segments that are angled from a direction parallel to the x-axis based in part on a predetermined angle. Adjacent storage elements can be positioned at respective ends of an angled segment of a wordline to facilitate increasing the distance between such storage elements, as compared to the distance between storage elements associated with an orthogonal memory array, where the increase in distance can be based in part on the predetermined angle. The size of the memory array can be the same or substantially the same size, as compared to an orthogonal memory array.Type: ApplicationFiled: December 14, 2007Publication date: June 18, 2009Applicant: SPANSION LLCInventors: Suketu Parikh, Vidyut Gopal, Brad Davis
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Publication number: 20080157199Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.Type: ApplicationFiled: March 16, 2007Publication date: July 3, 2008Inventors: Vidyut Gopal, Shankar Sinha, Jean Yee-Mei Yang, Phillip L. Jones
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Publication number: 20080160764Abstract: A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Inventors: David MATSUMOTO, Michael BRENNAN, Vidyut GOPAL, Jean YANG
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Publication number: 20080096388Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.Type: ApplicationFiled: October 20, 2006Publication date: April 24, 2008Applicants: Advanced Micro Devices, Inc., Spansion LLCInventors: David Matsumoto, Vidyut Gopal
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Publication number: 20070059948Abstract: Embodiments of the invention provide methods for forming hafnium materials, such as oxides and nitrides, by sequentially exposing a substrate to hafnium precursors and active oxygen or nitrogen species (e.g., ozone, oxygen radicals, or nitrogen radicals). The deposited hafnium materials have significantly improved uniformity when deposited by these atomic layer deposition (ALD) processes. In one embodiment, an ALD chamber contains an expanding channel having a bottom surface that is sized and shaped to substantially cover a substrate positioned on a substrate pedestal. During an ALD process for forming hafnium materials, process gases form a vortex flow pattern while passing through the expanding channel and sweep across the substrate surface. The substrate is sequentially exposed to chemical precursors that are pulsed into the process chamber having the vortex flow.Type: ApplicationFiled: May 31, 2006Publication date: March 15, 2007Inventors: Craig Metzner, Shreyas Kher, Vidyut Gopal, Shixue Han, Shankarram Athreya
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Publication number: 20060223339Abstract: Methods of forming metal compounds such as metal oxides or metal nitrides by sequentially introducing and then reacting metal organic compounds with ozone one or with oxygen radicals or nitrogen radicals formed in a remote plasma chamber. The metal compounds have surprisingly and significantly improved uniformity when deposited by atomic layer deposition with cycle times of at least 10 seconds. The metal compounds also do not contain detectable carbon when the metal organic compound is vaporized at process conditions in the absence of solvents or excess ligands.Type: ApplicationFiled: May 31, 2006Publication date: October 5, 2006Inventors: Craig Metzner, Shreyas Kher, Vidyut Gopal, Shixue Han, Shankarram Athreya
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Patent number: 7067439Abstract: Methods of forming metal compounds such as metal oxides or metal nitrides by sequentially introducing and then reacting metal organic compounds with ozone or with oxygen radicals or nitrogen radicals formed in a remote plasma chamber. The metal compounds have surprisingly and significantly improved uniformity when deposited by atomic layer deposition with cycle times of at least 10 seconds. The metal compounds also do not contain detectable carbon when the metal organic compound is vaporized at process conditions in the absence of solvents or excess ligands.Type: GrantFiled: September 19, 2002Date of Patent: June 27, 2006Assignee: Applied Materials, Inc.Inventors: Craig R. Metzner, Shreyas S. Kher, Vidyut Gopal, Shixue Han, Shankarram A. Athreya
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Patent number: 6887732Abstract: Microstructure devices, methods of forming a microstructure device and a method of forming a MEMS device are described. According to one aspect, a microstructure device includes: a semiconductive substrate; a monolithic microstructure device feature coupled with the semiconductive substrate, and wherein at least a portion of the microstructure device feature is configured to move relative to the semiconductive substrate; and a conductive structure provided directly upon the microstructure device feature.Type: GrantFiled: May 7, 2001Date of Patent: May 3, 2005Assignee: Applied Materials, Inc.Inventors: Vidyut Gopal, Jeffrey D. Chinn
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Patent number: 6666979Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.Type: GrantFiled: October 29, 2001Date of Patent: December 23, 2003Assignee: Applied Materials, Inc.Inventors: Jeffrey D. Chinn, Vidyut Gopal, Sofiane Soukane, Toi Yue Becky Leung
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Publication number: 20030232511Abstract: Methods of forming metal compounds such as metal oxides or metal nitrides by sequentially introducing and then reacting metal organic compounds with ozone or with oxygen radicals or nitrogen radicals formed in a remote plasma chamber. The metal compounds have surprisingly and significantly improved uniformity when deposited by atomic layer deposition with cycle times of at least 10 seconds. The metal compounds also do not contain detectable carbon when the metal organic compound is vaporized at process conditions in the absence of solvents or excess ligands.Type: ApplicationFiled: September 19, 2002Publication date: December 18, 2003Applicant: Applied Materials, Inc.Inventors: Craig R. Metzner, Shreyas S. Kher, Vidyut Gopal, Shixue Han, Shankarram A. Athreya