Patents by Inventor Vignesh Adhinarayanan
Vignesh Adhinarayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12353715Abstract: A method includes, in response to receiving a command from a processing device, reading original data from a set of one or more memory devices based on an address range specified in the command, and transmitting a subset of the original data to the processing device, where the subset includes fewer zero values than the original data.Type: GrantFiled: September 30, 2021Date of Patent: July 8, 2025Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan
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Publication number: 20250130715Abstract: A system includes memory hardware including a memory and a processing-in-memory component. A system includes a host including at least one core. A system includes a memory controller including a scheduling system. The scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. The scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.Type: ApplicationFiled: October 18, 2023Publication date: April 24, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Shaizeen Dilawarhusen Aga
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Patent number: 12210398Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.Type: GrantFiled: July 3, 2023Date of Patent: January 28, 2025Inventors: Vedula Venkata Srikant Bharadwaj, Shomit N. Das, Anthony T. Gutierrez, Vignesh Adhinarayanan
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Patent number: 12197735Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.Type: GrantFiled: March 31, 2023Date of Patent: January 14, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
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Publication number: 20250006232Abstract: An apparatus and method for creating less computationally intensive nodes for a neural network. An integrated circuit includes a host processor and multiple memory channels, each with multiple memory array banks. Each of the memory array banks includes components of a processing-in-memory (PIM) accelerator and a scatter and gather circuit used to dynamically perform quantization operations and dequantization operations that offload these operations from the host processor. The host processor executes a data model that represents a neural network. The memory array banks store a single copy of a particular data value in a single precision. Therefore, the memory array banks avoid storing replications of the same data value with different precisions to be used by a neural network node. The memory array banks dynamically perform quantization operations and dequantization operations on one or more of the weight values, input data values, and activation output values of the neural network.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Inventors: Ioannis Papadopoulos, Vignesh Adhinarayanan, Ashwin Aji, Jagadish B. Kotra
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Publication number: 20240395289Abstract: Integrated circuit (IC) memory devices and methods for fabricating the same are provided. In one example, an integrated circuit (IC) memory device is provided that includes a substrate, at least two or more memory (IC) dies, and a non-memory IC die integrated in a chip package. The memory (IC) dies are stacked on the substrate to form a memory die stack. The non-memory IC die contains row segmentation logic having an output routed to corresponding wordline drivers of the memory IC dies through vertical wiring passing through the memory die stack.Type: ApplicationFiled: May 22, 2024Publication date: November 28, 2024Inventors: Vignesh ADHINARAYANAN, Hyung-Dong LEE, Bradford BECKMANN, Seyedmohammad SEYEDZADEHDELCHEH, Sergey BLAGODUROV
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Publication number: 20240329847Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
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Publication number: 20240329846Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
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Patent number: 12086418Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.Type: GrantFiled: March 31, 2023Date of Patent: September 10, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
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Publication number: 20240088099Abstract: Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory IC die is stacked on the first memory IC die. Bitlines are routed through the first and second IC dies in a substantially vertical orientation. Wordlines within the first memory IC die are oriented orthogonal to the bitlines.Type: ApplicationFiled: June 28, 2023Publication date: March 14, 2024Inventors: Divya Madapusi Srinivas PRASAD, Vignesh ADHINARAYANAN, Michael IGNATOWSKI, Hyung-Dong LEE
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Publication number: 20240078017Abstract: A data processing system includes a data processor and a memory controller receiving memory access requests from the data processor and generating at least one memory access cycle to a memory system in response to the receiving. The memory controller includes a command queue and a sparse element processor. The command queue is for receiving and storing the memory access requests including a first memory access request including a small element request. The sparse element processor is for causing the memory controller to issue a second memory access request to the memory system in response to the first memory access request with a density greater than a density indicated by the first memory access request.Type: ApplicationFiled: July 27, 2023Publication date: March 7, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Niti Madan, Marjan Fariborz
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Publication number: 20240004801Abstract: An encryption circuit includes an iterative block cipher circuit. The iterative block cipher circuit has a counter input for a row index, a key input for receiving a secret key, and an output for providing an encrypted counter value in response to performing a block cipher process using the row index as a counter the secret key. The encryption circuit uses the iterative block cipher circuit during a row operation to a memory.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Nuwan Jayasena, Shaizeen Dilawarhusen Aga, Vignesh Adhinarayanan
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Publication number: 20240004786Abstract: Allocating memory for processing-in-memory (PIM) devices, including: allocating, in a first Dynamic Random Access Memory (DRAM) sub-array, a first data structure beginning in a first grain of the DRAM; allocating, in a second DRAM sub-array, a second data structure beginning in a second grain of the DRAM; and wherein the second DRAM sub-array is different from the first DRAM sub-array and the second grain is different from the first grain.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: VIGNESH ADHINARAYANAN, MAHZABEEN ISLAM, JAGADISH B. KOTRA, SERGEY BLAGODUROV
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Publication number: 20230420036Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.Type: ApplicationFiled: August 31, 2023Publication date: December 28, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
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Publication number: 20230350485Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Vedula Venkata Srikant Bharadwaj, Shomit Das, Anthony T. Gutierrez, Vignesh Adhinarayanan
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Patent number: 11756606Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.Type: GrantFiled: December 13, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
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Patent number: 11726546Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.Type: GrantFiled: September 25, 2020Date of Patent: August 15, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Vedula Venkata Srikant Bharadwaj, Shomit N. Das, Anthony T. Gutierrez, Vignesh Adhinarayanan
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Publication number: 20230186976Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
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Publication number: 20230102690Abstract: A method includes, in response to receiving a command from a processing device, reading original data from a set of one or more memory devices based on an address range specified in the command, and transmitting a subset of the original data to the processing device, where the subset includes fewer zero values than the original data.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan
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Publication number: 20220100257Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Vedula Venkata Srikant Bharadwaj, Shomit N. Das, Anthony T. Gutierrez, Vignesh Adhinarayanan