Abstract: Multiplication circuitry comprises adder sub-arrays which each add partial products derived from first/second operands. Sub-array result values generated by the adder sub-arrays are added in a result assembly addition to generate at least one multiplication result value representing a result of signed multiplication of the first operand and the second operand. Sign extension emulation is performed for a sign-extension-emulated sub-array result value added in the result assembly addition, by applying a default zero extension to the sign-extension-emulated sub-array result value regardless of its sign and emulating an effect of sign extending the sign-extension-emulated sub-array result value using another of the assembled values.

Abstract: An apparatus has processing circuitry with at least two replicated computation blocks. Each computation block performs a particular calculation based on a respective input value to produce a respective output value to be used as a result of the calculation. The apparatus also has storage circuitry arranged on output paths of the computation blocks to store the output values of the computation blocks. The processing circuitry is operable in a fault detection mode in which the processing circuitry latches the output values of the computation blocks in the storage circuitry and presents, as the result of the calculations, the stored values.