Abstract: An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.

Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes memory access circuitry and processing circuitry coupled to the memory access circuitry. The memory access circuitry is configured to receive a read request corresponding to a set of instructions for execution by processing circuitry stored in non-volatile memory, determine whether to preempt current access to the non-volatile memory corresponding to one or more access requests in favor of the read request based on a priority of the read request relative to the one or more access requests, obtain the set of instructions from the non-volatile memory, and supply the set of instructions to the processing circuitry. The processing circuitry executes the set of instructions.

Abstract: An example device includes: a compute core configured to: send a first request to flash manager circuitry, the first request to store write data in a flash memory; and send a second request to the flash manager circuitry, the second request sent after the first request, the second request to transfer an XIP read operation to the flash memory; the flash manager circuitry configured to: receive the first request; transmit the write data to the flash memory for storing in the flash memory; receive the second request before the storing of the write data is complete; determine whether to preempt the storing of the write data, transmit, in response to a determination to preempt, the XIP read operation to the flash; and the flash memory configured to provide data to the compute core based on the transmitted XIP read operation.

Abstract: Systems, apparatus, articles of manufacture, and methods to animate a splash screen are disclosed. An example apparatus includes a display controller; communication circuitry coupled to the display controller, memory controller circuitry configured to couple to a first memory and a second memory, and programmable circuitry coupled to the communication circuitry and the memory controller circuitry and configured to: receive an indication from the display controller to load a frame, in response to the indication from the display controller, cause the memory controller circuitry to copy the frame from the first memory to the second memory, update a frame pointer used by the display controller to reference the frame, and cause the display controller to output the frame to a display circuit.

Abstract: An example device includes: a compute core configured to: send a first request to flash manager circuitry, the first request to store write data in a flash memory; and send a second request to the flash manager circuitry, the second request sent after the first request, the second request to transfer an XIP read operation to the flash memory; the flash manager circuitry configured to: receive the first request; transmit the write data to the flash memory for storing in the flash memory; receive the second request before the storing of the write data is complete; determine whether to preempt the storing of the write data, transmit, in response to a determination to preempt, the XIP read operation to the flash; and the flash memory configured to provide data to the compute core based on the transmitted XIP read operation.