Abstract: Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

Abstract: Systems and methods related to instruction caching schemes are disclosed herein. A set of leading groups of bits in a set of instructions from a cache may be evaluated, in parallel and using a pre-decoder circuit, at a set of locations in the set of instructions. The set of locations may be spaced apart by a length of the smallest expected instruction and the lengths of the expected instructions may be multiples of the length of the smallest expected instruction. A set of instruction sizes associated with the set of locations may be determined from the set of leading groups of bits and stored in a set of entries in a pre-decoded instruction cache. The instructions may be decoded using a decoder circuit and the set of entries. The pre-decoded instruction cache and the pre-decoding processes may reduce the latency of decoding instructions.

Abstract: Systems and methods related to one or more processors with dispatch buffer allocation affinity credit adjustment are disclosed herein. An instruction decoder and dispatch unit may have multiple dispatch buffers to which they may distribute instructions. Instruction pipelines may utilize a credits-based analysis to assign instructions to specific dispatch buffers based on various factors such as instruction affinity, resource requirements, execution characteristics, the affinities serviced by specific dispatch buffers, the cumulativeness of instruction affinities, availability in the dispatch buffers, the number of instructions that have been assigned to each dispatch buffer, and other factors. One instruction may affect the credits of another instruction.

Abstract: Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

Abstract: Systems and methods related to branch prediction circuits and instruction fetch circuits in computer processors are disclosed herein. A branch prediction circuit and an instruction fetch circuit may operate in combination to fetch a group of instructions from a memory. A counter and an offset may be associated with the fetch group and may form a prediction entry in a table of a prediction circuit. The counter may represent the longest consecutive number of uses of an instruction as the exit point of the branch. The offset may represent the instruction in the fetch group that is associated with the current longest consecutive number of uses as the exit point of the branch. The processor may predict that a branching instruction in the fetch group will be used to branch the program based on the counter and the offset. The fetch circuit may prefetch an instruction based on the prediction.

Abstract: Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.