Patents by Inventor Vijai Komar N. Chhagan

Vijai Komar N. Chhagan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to fabricate a floating gate with a sloping sidewall for a flash memory
    Publication number: 20020000604
    Abstract: A method to fabricate a floating gate with a sloping sidewall for a Flash Memory is described. Field oxide isolation regions are provided in the substrate. A silicon oxide layer is provided overlying the isolation regions and the substrate. A first polysilicon layer is deposited overlying the silicon oxide layer. A photoresist layer is deposited overlying the first polysilicon layer. The photoresist layer is etched to remove sections of the photoresist as defined by photolithographic process. The photoresist layer, the first polysilicon layer, and the silicon oxide layer are etched in areas uncovered by the photoresist layer to create structures with sloping sidewall edges. The photoresist layer is etched away. An interpoly dielectric layer is deposited overlying the structures, the sloping sidewall edges, and the isolation regions. A second polysilicon layer is deposited overlying the interpoly dielectric and the fabrication of the integrated circuit device is completed.
    Type: Application
    Filed: August 2, 2001
    Publication date: January 3, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Vijai Komar N. Chhagan, Yelehanka Ramachandramurthy Pradeep, Zhou Mei Sheng, Henry Gerung
  • Method to fabricate a floating gate with a sloping sidewall for a flash memory
    Patent number: 6284637
    Abstract: A method to fabricate a floating gate with a sloping sidewall for a Flash Memory is described. Field oxide isolation regions are provided in the substrate. A silicon oxide layer is provided overlying the isolation regions and the substrate. A first polysilicon layer is deposited overlying the silicon oxide layer. A photoresist layer is deposited overlying the first polysilicon layer. The photoresist layer is etched to remove sections of the photoresist as defined by photolithographic process. The photoresist layer, the first polysilicon layer, and the silicon oxide layer are etched in areas uncovered by the photoresist layer to create structures with sloping sidewall edges. The photoresist layer is etched away. An interpoly dielectric layer is deposited overlying the structures, the sloping sidewall edges, and the isolation regions. A second polysilicon layer is deposited overlying the interpoly dielectric and the fabrication of the integrated circuit device is completed.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: September 4, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Vijai Komar N. Chhagan, Yelehanka Machandramurthy Pradee, Mei Sheng Zhou, Henry Gerung