Patents by Inventor Vijakomar Chhagan

Vijakomar Chhagan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6300251
    Abstract: A method for anisotropically etching a partially manufactured semiconductor structure, more specifically, a stacked FET gate structure containing a bottom anti-reflective coating (Barc) layer is described. The structure is covered with a photoresist layer which is patterned to defines the gate region. The processing chemistry is predominantly carbon tetrafluoride, (CF4) with the inclusion of chlorine (Cl2) where fluorine (F) is generated in the plasma as the etchant for the structure. During processing, the wafer is cooled with helium (He) that lowers the wafer temperature and promotes sidewall deposition from the fluorine species which acts as a passivation layer producing a anisotropic or vertical etch profile. The process reduces etch time and results in very repeatable end point control of the Bark etch and poly cap etch improving the control of the structure critical dimensions and improving process throughput. The reduction in the use of fluorine based species reduces any potential environmental impact.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: October 9, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yelehanka Ramachandramurthy Pradeep, Vijakomar Chhagan, Henry Gerung