Patents by Inventor Vijay Balakrishnan
Vijay Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240020009Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.Type: ApplicationFiled: September 20, 2023Publication date: January 18, 2024Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
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Publication number: 20230379141Abstract: A programmable data storage device includes: a non-volatile memory; a storage controller configured to control the non-volatile memory; a network interface; and a field programmable gate array configured to: implement a blockchain algorithm; and store at least one block of a blockchain corresponding to the blockchain algorithm in the non-volatile memory via the storage controller; and a processor having memory coupled thereto, the memory having instructions stored thereon that, when executed by the processor, cause the processor to: send and receive one or more blocks of the blockchain via the network interface; and control the field programmable gate array to execute the blockchain algorithm on the one or more blocks of the blockchain.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Inventors: Rajinikanth Pandurangan, Vijay Balakrishnan
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Patent number: 11768601Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.Type: GrantFiled: June 9, 2021Date of Patent: September 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
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Patent number: 11750370Abstract: A programmable data storage device includes: a non-volatile memory; a storage controller configured to control the non-volatile memory; a network interface; and a field programmable gate array configured to: implement a blockchain algorithm; and store at least one block of a blockchain corresponding to the blockchain algorithm in the non-volatile memory via the storage controller; and a processor having memory coupled thereto, the memory having instructions stored thereon that, when executed by the processor, cause the processor to: send and receive one or more blocks of the blockchain via the network interface; and control the field programmable gate array to execute the blockchain algorithm on the one or more blocks of the blockchain.Type: GrantFiled: December 22, 2020Date of Patent: September 5, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Rajinikanth Pandurangan, Vijay Balakrishnan
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Patent number: 11392297Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data and may support a plurality of device streams. A SSD controller may manage reading and writing data to the flash memory, and may store a submission queue and a chunk-to-stream mapper. A flash translation layer may include a receiver to receive a write command, an LBA mapper to map an LBA to a chunk identifier (ID), stream selection logic to select a stream ID based on the chunk ID, a stream ID adder to add the stream ID to the write command, a queuer to place the chunk ID in the submission queue, and background logic to update the chunk-to-stream mapper after the chunk ID is removed from the submission queue.Type: GrantFiled: April 22, 2020Date of Patent: July 19, 2022Inventors: Jingpei Yang, Changho Choi, Rajinikanth Pandurangan, Vijay Balakrishnan, Ramaraj Pandian
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Patent number: 11314441Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.Type: GrantFiled: May 15, 2020Date of Patent: April 26, 2022Inventors: Narges Shahidi, Manu Awasthi, Tameesh Suri, Vijay Balakrishnan
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Publication number: 20210294494Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.Type: ApplicationFiled: June 9, 2021Publication date: September 23, 2021Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
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Patent number: 11112972Abstract: A method includes: receiving, at an acceleration platform manager (APM) from an application service manager (ASM), application function processing information; allocating, by the APM, a first storage processing accelerator (SPA) from a plurality of SPAs, wherein at least one SPA of the plurality of SPAs comprises a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs comprising n SPEs, enabling the plurality of SPEs in the first SPA, wherein once enabled, the at least one SPE of the plurality of SPEs in the first SPA is configured to process data based on the application function processing information; determining, by the APM, if data processing is completed by the at least one SPE of the plurality of SPEs in the first SPA; and sending, by the APM, a result of the data processing by the SPEs of the first SPA, to the ASM.Type: GrantFiled: February 6, 2019Date of Patent: September 7, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
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Patent number: 11061574Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.Type: GrantFiled: February 7, 2019Date of Patent: July 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
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Publication number: 20210111868Abstract: A programmable data storage device includes: a non-volatile memory; a storage controller configured to control the non-volatile memory; a network interface; and a field programmable gate array configured to: implement a blockchain algorithm; and store at least one block of a blockchain corresponding to the blockchain algorithm in the non-volatile memory via the storage controller; and a processor having memory coupled thereto, the memory having instructions stored thereon that, when executed by the processor, cause the processor to: send and receive one or more blocks of the blockchain via the network interface; and control the field programmable gate array to execute the blockchain algorithm on the one or more blocks of the blockchain.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Inventors: Rajinikanth Pandurangan, Vijay Balakrishnan
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Patent number: 10956294Abstract: A system and method of generating representative I/O. The system is configured to utilize representative I/O patterns stored in a pattern database. A user may select one or more patterns to perform I/O using. The patterns are modified according to user supplied parameters and multiple parameters are integrated into a single workload. I/O is then generated according to the workload and system performance may be measured.Type: GrantFiled: December 22, 2017Date of Patent: March 23, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Janki Sharadkumar Bhimani, Rajinikanth Pandurangan, Vijay Balakrishnan, Changho Choi
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Patent number: 10949341Abstract: According to one general aspect, an apparatus may include a storage memory to store a plurality of key-value pairs. The apparatus may include at least one snapshot counter configured to store an operation number associated with a respective snapshot of the plurality of key-value pairs. The apparatus may include a snapshot data structure configured to identify, for at least one key-value pair, which, if any, snapshot(s) the respective key-value pair is associated with.Type: GrantFiled: November 1, 2018Date of Patent: March 16, 2021Inventors: Anahita Shayesteh, Jingpei Yang, Vijay Balakrishnan
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Patent number: 10901907Abstract: A method for providing a Bloom filter for a multi-stream enabled solid-state drive (SSD) is disclosed. The Bloom filter includes two Bloom filter arrays, a counter corresponding to the two Bloom filter arrays, and a masking logic. The method includes: inserting an element in one or more of the two Bloom filter arrays using a plurality of hash functions; and updating the counter based on the insertion of the element. The method further includes: updating the Bloom filter by inserting one or more additional elements in one or more of the two Bloom filter arrays and updating the counter; and masking a data stored in the Bloom filter with the one or more additional elements to pseudo delete the data using the masking logic and reduce a false positive rate of the Bloom filter.Type: GrantFiled: February 13, 2018Date of Patent: January 26, 2021Inventors: Janki Bhimani, Rajinikanth Pandurangan, Vijay Balakrishnan, Changho Choi
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Patent number: 10880071Abstract: A programmable data storage device includes: a non-volatile memory; a storage controller configured to control the non-volatile memory; a network interface; and a field programmable gate array configured to: implement a blockchain algorithm; and store at least one block of a blockchain corresponding to the blockchain algorithm in the non-volatile memory via the storage controller; and a processor having memory coupled thereto, the memory having instructions stored thereon that, when executed by the processor, cause the processor to: send and receive one or more blocks of the blockchain via the network interface; and control the field programmable gate array to execute the blockchain algorithm on the one or more blocks of the blockchain.Type: GrantFiled: May 16, 2018Date of Patent: December 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Rajinikanth Pandurangan, Vijay Balakrishnan
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Publication number: 20200364229Abstract: A solid state drive (SSD) is disclosed. The SSD may include flash memory to store data and an SSD controller to manage reading data from and writing data to the flash memory. The SSD may also include a field programmable gate array (FPGA) operative to perform a comparison of a search sequence with a reference sequence, where the reference sequence is stored in the flash memory. The FPGA may: identify a continuous match of atoms between the search sequence and the reference sequence; divide the search sequence into a left portion of the search sequence that includes atoms before the continuous match of atoms in the search sequence, a center portion of the search sequence that includes the continuous match of atoms in the search sequence, and a right portion of the search sequence that includes atoms after the continuous match of atoms in the search sequence; match the left portion of the search sequence with the reference sequence; and match the right portion of the search sequence with the reference sequence.Type: ApplicationFiled: August 26, 2019Publication date: November 19, 2020Inventors: Salvatore ARCURI, Stephen FISCHER, Vijay BALAKRISHNAN, Anahita SHAYESTEH, Ramdas P. KACHARE, Jason MARTINEAU, Yasser ZAGHLOUL
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Publication number: 20200278805Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.Type: ApplicationFiled: May 15, 2020Publication date: September 3, 2020Inventors: Narges SHAHIDI, Manu AWASTHI, Tameesh SURI, Vijay BALAKRISHNAN
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Publication number: 20200249839Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data and may support a plurality of device streams. A SSD controller may manage reading and writing data to the flash memory, and may store a submission queue and a chunk-to-stream mapper. A flash translation layer may include a receiver to receive a write command, an LBA mapper to map an LBA to a chunk identifier (ID), stream selection logic to select a stream ID based on the chunk ID, a stream ID adder to add the stream ID to the write command, a queuer to place the chunk ID in the submission queue, and background logic to update the chunk-to-stream mapper after the chunk ID is removed from the submission queue.Type: ApplicationFiled: April 22, 2020Publication date: August 6, 2020Inventors: Jingpei YANG, Changho CHOI, Rajinikanth PANDURANGAN, Vijay BALAKRISHNAN, Ramaraj PANDIAN
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Patent number: 10732905Abstract: A method of selecting among a plurality of I/O streams through which data is to be written to a multi-streaming flash storage device is presented. According to an example embodiment, the method comprises: assigning write sequences of similar length to the same I/O streams; receiving instructions for a write operation, the instructions including a starting logical block address (LBA) and a number of blocks of data to be written; determining whether the write operation is part of an existing write sequence; identifying an I/O stream associated with an existing write sequence; and providing a stream ID of the identified I/O stream to the multi-streaming flash storage device.Type: GrantFiled: April 4, 2019Date of Patent: August 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sina Hassani, Anahita Shayesteh, Vijay Balakrishnan
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Patent number: 10719354Abstract: A system for scheduling the execution of container workloads from a series of applications and a series of containers of each application. The system includes a processor and a non-transitory computer-readable storage medium having instructions stored thereon, which, when executed by the processor, cause the system to calculate a conflict penalty matrix including a conflict penalty for each potential combination of container workloads of the plurality of containers, and calculate a minimum total conflict penalty of the container workloads and a number of workload batches for executing the container workloads. The number of workload batches is associated with the minimum total conflict penalty. The instructions, when executed by the processor, further cause the system to assign the container workloads to the workload batches based on the minimum total conflict penalty and the number of the workload batches.Type: GrantFiled: November 22, 2017Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Janki Sharadkumar Bhimani, Anand Subramanian, Jingpei Yang, Vijay Balakrishnan
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Publication number: 20200183583Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.Type: ApplicationFiled: February 7, 2019Publication date: June 11, 2020Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz