Patents by Inventor Vijay Dhanraj
Vijay Dhanraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11593154Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.Type: GrantFiled: December 20, 2018Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Ahmad Samih, Rajshree Chabukswar, Russell Fenger, Shadi Khasawneh, Vijay Dhanraj, Muhammad Abozaed, Mukund Ramakrishna, Atsuo Kuwahara, Guruprasad Settuvalli, Eugene Gorbatov, Monica Gupta, Christine M. Lin
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Patent number: 11422849Abstract: A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.Type: GrantFiled: August 22, 2019Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Deepak Samuel Kirubakaran, Vijay Dhanraj, Russell Jerome Fenger, Hisham Abu-Salah, Eliezer Weissmann
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Patent number: 11194381Abstract: Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.Type: GrantFiled: September 29, 2017Date of Patent: December 7, 2021Assignee: INTEL CORPORATIONInventors: Abhinav Karhu, Russell Fenger, Vijay Dhanraj, Balaji Masanamuthu Chinnathurai
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Patent number: 11073060Abstract: A method for optimizing an active regeneration of a diesel particulate filter of a motor vehicle, including the following steps: First, information regarding the planned travel route of the motor vehicle is ascertained; subsequently, a query is made as to whether the remaining travel time is less than the time needed for an upcoming regeneration of the diesel particulate filter, and/or a query is made as to whether the following engine phase of the motor vehicle is an overrun phase; and the active regeneration of the diesel particulate filter is prevented, if the remaining travel time is less than the time needed for an upcoming regeneration of the diesel particulate filter, or if the following engine phase is an overrun phase.Type: GrantFiled: June 1, 2016Date of Patent: July 27, 2021Assignee: Robert Bosch GmbHInventor: Vijay Dhanraj
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Publication number: 20210055958Abstract: A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Inventors: Deepak Samuel Kirubakaran, Vijay Dhanraj, Russell Jerome Fenger, Hisham Abu-Salah, Eliezer Weissmann
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Patent number: 10915356Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.Type: GrantFiled: August 30, 2018Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Ramakrishnan Sivakumar, Vijay Dhanraj, Russell Fenger, Guy Therien
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Publication number: 20200356156Abstract: Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2017Publication date: November 12, 2020Applicant: INTEL CORPORATIONInventors: Abhinav KARHU, Russell FENGER, Vijay DHANRAJ, Balaji MASANAMUTHU CHINNATHURAI
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Publication number: 20200272513Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.Type: ApplicationFiled: January 13, 2020Publication date: August 27, 2020Inventors: Avinash N. Ananthakrishnan, Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov, Stephen H. Gunther, Monica Gupta, Efraim Rotem, Krishnakanth V. Sistla, Guy M. Therien, Ankush Varma, Eliezer Weissmann
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Publication number: 20200201671Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: AHMAD SAMIH, RAJSHREE CHABUKSWAR, Russell Fenger, Shadi Khasawneh, Vijay Dhanraj, Muhammad Abozaed, Mukund Ramakrishna, Atsuo Kuwahara, Guruprasad Settuvalli, Eugene Gorbatov, MONICA GUPTA, CHRISTINE M. LIN
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Patent number: 10545793Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.Type: GrantFiled: September 29, 2017Date of Patent: January 28, 2020Assignee: Intel CorporationInventors: Avinash N. Ananthakrishnan, Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov, Stephen H. Gunther, Monica Gupta, Efraim Rotem, Krishnakanth V. Sistla, Guy M. Therien, Ankush Varma, Eliezer Weissmann
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Patent number: 10503550Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.Type: GrantFiled: September 30, 2017Date of Patent: December 10, 2019Assignee: Intel CorporationInventors: Monica Gupta, Russell J. Fenger, Vijay Dhanraj, Deepak Samuel Kirubakaran, Srividya Ambale, Israel Hirsh, Eliezer Weissmann, Hisham Abu Salah
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Patent number: 10372493Abstract: Apparatuses, methods and storage medium associated with scheduling of threads and/or virtual machines, are disclosed herein. In embodiments, an apparatus is provided with a scheduler of an operating system and/or a virtual machine monitor. The scheduler is to retrieve or receive capabilities of the cores of one or more multi-core processors of the apparatus with diverse capabilities, and schedule a plurality of threads for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and characteristics of the plurality of threads. The virtual machine monitor is to retrieve or receive capabilities of the cores, and schedule a plurality of virtual machines for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and respective priorities of the virtual machines. Other embodiments may be described and/or claimed.Type: GrantFiled: December 22, 2015Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Vijay Dhanraj, Gaurav Khanna, Russell J. Fenger, Monica Gupta
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Publication number: 20190102227Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Avinash Ananthakrishnan, Vijay Dhanraj, Russell Fenger, Vivek Garg, Eugene Gorbatov, Stephen Gunter, Monica Gupta, Efraim Rotem, Krishnakanth Sistla, Guy Therien, Ankush Verma, Eliezer Weissmann
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Publication number: 20190102229Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.Type: ApplicationFiled: September 30, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: Monica Gupta, Russell J. Fenger, Vijay Dhanraj, Deepak Samuel Kirubakaran, Srividya Ambale, Israel Hirsh, Eliezer Weissmann, Hisham Abu-Salah
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Publication number: 20190102221Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Avinash N. Ananthakrishnan, Vijay Dhanraj, Russell J. Fenger, Vivek Garg, Eugene Gorbatov, Stephen H. Gunter, Monica Gupta, Efraim Rotem, Krishnakanth V. Sistla, Guy M. Therien, Ankush Varma, Eliezer Weissmann
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Publication number: 20190042307Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.Type: ApplicationFiled: August 30, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Ramakrishnan Sivakumar, Vijay Dhanraj, Russell Fenger, Guy Therien
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Publication number: 20190003365Abstract: A method for optimizing an active regeneration of a diesel particulate filter of a motor vehicle, including the following steps: First, information regarding the planned travel route of the motor vehicle is ascertained; subsequently, a query is made as to whether the remaining travel time is less than the time needed for an upcoming regeneration of the diesel particulate filter, and/or a query is made as to whether the following engine phase of the motor vehicle is an overrun phase; and the active regeneration of the diesel particulate filter is prevented, if the remaining travel time is less than the time needed for an upcoming regeneration of the diesel particulate filter, or if the following engine phase is an overrun phase.Type: ApplicationFiled: June 1, 2016Publication date: January 3, 2019Inventor: Vijay Dhanraj
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Publication number: 20180211537Abstract: A method for braking a vehicle, including supplying surroundings data of the vehicle to a braking device; and generating control signals of a brake by using the surroundings data; the surroundings data of the vehicle being provided by a server unit located outside of the vehicle.Type: ApplicationFiled: January 22, 2018Publication date: July 26, 2018Inventor: Vijay Dhanraj
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Publication number: 20170177415Abstract: Apparatuses, methods and storage medium associated with scheduling of threads and/or virtual machines, are disclosed herein. In embodiments, an apparatus is provided with a scheduler of an operating system and/or a virtual machine monitor. The scheduler is to retrieve or receive capabilities of the cores of one or more multi-core processors of the apparatus with diverse capabilities, and schedule a plurality of threads for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and characteristics of the plurality of threads. The virtual machine monitor is to retrieve or receive capabilities of the cores, and schedule a plurality of virtual machines for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and respective priorities of the virtual machines. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: Vijay DHANRAJ, Gaurav KHANNA, Russell J. FENGER, Monica GUPTA
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Publication number: 20160371118Abstract: Apparatuses, methods and storage media associated with managing operations of a virtual machine including dynamic idling and scheduling of virtual processors on logical processors described herein. In embodiments, an apparatus may include a physical computing platform with one or more physical processors, a virtual machine manager to manage operation of virtual machines each with a priority level and with one or more virtual processors that operate on logical processor instances of the one or more physical processors, wherein the virtual machine manager tracks activities of the virtual processors that operate on a shared logical processor instance and selectively idles and schedules one or more virtual processors in view of at least the activities of the virtual processors that operate on a shared logical processor instance and the priority of the virtual machines associated with the one or more virtual processors.Type: ApplicationFiled: June 17, 2015Publication date: December 22, 2016Inventors: Vijay Dhanraj, Abhinav R. Karhu, Gaurav Khanna, Russell J. Fenger