Patents by Inventor Vijay G. Ullal

Vijay G. Ullal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package including a semiconductor die and a capacitive component
    Patent number: 9478519
    Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 25, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ahmad R. Ashrafzadeh, Vijay G. Ullal, Justin Chiang, Daniel Kinzer, Michael M. Dube, Oseob Jeon, Chung-Lin Wu, Maria Cristina Estacio
  • PACKAGE INCLUDING A SEMICONDUCTOR DIE AND A CAPACITIVE COMPONENT
    Publication number: 20160126219
    Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 5, 2016
    Inventors: Ahmad R. ASHRAFZADEH, Vijay G. ULLAL, Justin CHIANG, Daniel KINZER, Michael M. DUBE, Oseob JEON, Chung-Lin WU, Maria Cristina ESTACIO
  • Apparatus related to an improved package including a semiconductor die
    Patent number: 9177925
    Abstract: In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: November 3, 2015
    Assignee: Fairfchild Semiconductor Corporation
    Inventors: Ahmad R. Ashrafzadeh, Vijay G. Ullal, Justin Chiang, Daniel Kinzer, Michael M. Dube, Oseob Jeon, Chung-Lin Wu, Maria Cristina Estacio