Patents by Inventor Vijay K. Nagasamy

Vijay K. Nagasamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5526277
    Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.
    Type: Grant
    Filed: December 13, 1994
    Date of Patent: June 11, 1996
    Assignee: LSI Logic Corporation
    Inventors: Carlos Dangelo, Vijay K. Nagasamy, Ahsan Bootehsaz, Sreeranga P. Rajan
  • Patent number: 5222030
    Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.
    Type: Grant
    Filed: April 6, 1990
    Date of Patent: June 22, 1993
    Assignee: LSI Logic Corporation
    Inventors: Carlos Dangelo, Vijay K. Nagasamy, Ahsan Bootehsaz, Sreeranga P. Rajan