Abstract: An integrated circuit with a LV transistor and a high performance asymmetric transistor. A power amplifier integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming an integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming a power amplifier integrated circuit with an nmos core transistor and an nmos high performance asymmetric transistor, a resistor, and an inductor.

Abstract: A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing (102) is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed (103) including electrically stressing for a time (t).

Abstract: A method for evaluating gate dielectrics (100) includes providing a test structure (101). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing (102) is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed (103) including electrically stressing for a time (t).

Abstract: A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.

Abstract: A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.

Abstract: A method is provided of correlating integrated circuit NBTI-induced performance degradation to discrete transistor NBTI-induced performance degradation and using that correlation to estimate integrated circuit degradation over time using test results based on a discrete transistor. Because discrete transistors are easier and cheaper to test, the technique described herein makes it easier, faster and cheaper to estimate the degradation of an integrated circuit over time than testing the integrated circuit itself.