Abstract: Die-to-die interconnect structures are leveraged to form the inductive component of an LC oscillator, thus yielding an LC tank distributed across multiple IC dies rather than lumped in a single die. By this arrangement, reliance on area/power-consuming on-chip inductors may be reduced or eliminated, and phase-aligned clocks may be extracted from the LC tank within each of the spanned IC dies, obviating multiple oscillator instances or complex phase alignment circuitry.

Abstract: Die-to-die interconnect structures are leveraged to form the inductive component of an LC oscillator, thus yielding an LC tank distributed across multiple IC dies rather than lumped in a single die. By this arrangement, reliance on area/power-consuming on-chip inductors may be reduced or eliminated, and phase-aligned clocks may be extracted from the LC tank within each of the spanned IC dies, obviating multiple oscillator instances or complex phase alignment circuitry.

Abstract: A circuit for driving a laser diode has a variable bias circuit. The variable bias circuit has an output designed to couple to the laser diode. A modulation circuit has an output designed to couple to the laser diode.

Abstract: A method, system, and apparatus are disclosed that correct a differential clock signal. A clock correction circuit may determine a DC correction for a first clock signal of a differential clock signal and a DC correction for a second clock signal of a differential clock signal based upon a DC level of the differential clock signal. The clock correction circuit may adjust a DC level of the first clock signal based upon the DC correction for the first clock signal and a DC level of the second clock signal based upon the DC correction for the second clock signal to substantially maintain a duty cycle of the differential clock signal.

Abstract: A method, system, and apparatus are disclosed that correct a differential clock signal. A clock correction circuit may determine a DC correction for a first clock signal of a differential clock signal and a DC correction for a second clock signal of a differential clock signal based upon a DC level of the differential clock signal. The clock correction circuit may adjust a DC level of the first clock signal based upon the DC correction for the first clock signal and a DC level of the second clock signal based upon the DC correction for the second clock signal to substantially maintain a duty cycle of the differential clock signal.

Abstract: A circuit, system, and method is provided for regulating the pulse width and/or duty cycle of a signal indirectly or directly used to drive, e.g., a transmitter. The load of the transmitter can be, for example, an optical signal transmitter. The circuit includes a feedback loop that adjusts the output signal so that the lower voltages are chopped at a reference voltage input into the driver. The magnitude of the reference voltage will regulate the pulse width of the output signal, as well as the duty cycle of the output signal. A low input voltage swing is well-suited to be operated upon by the driver circuit to produce a symmetric pulse width that is particularly adapted to high-speed optical data communication applications. The gain and slew rate of the feedback circuit and, predominantly, the comparator and pull-down transistor of the feedback circuit is tuned to ensure the pull-down transistor is always on and, therefore, the comparator will toggle, but within constrained (i.e., regulated) voltage limits.