Patents by Inventor Vijay Korthikanti

Vijay Korthikanti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896039
    Abstract: In one embodiment, a matrix operation may be performed on one or more matrix operands. For example, matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands. The one or more matrix operands may be extracted from the matrix data. A matrix routine associated with the matrix operation may be identified. The matrix routine may be executed on a matrix processor using the one or more matrix operands. A result of the matrix operation may be obtained based on the matrix routine executed by the matrix processor.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Tony L. Werner, Aravind Kalaiah, Vijay Korthikanti, Horace Lau
  • Publication number: 20190171450
    Abstract: In one embodiment, a matrix operation may be performed on one or more matrix operands. For example, matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands. The one or more matrix operands may be extracted from the matrix data. A matrix routine associated with the matrix operation may be identified. The matrix routine may be executed on a matrix processor using the one or more matrix operands. A result of the matrix operation may be obtained based on the matrix routine executed by the matrix processor.
    Type: Application
    Filed: January 31, 2019
    Publication date: June 6, 2019
    Applicant: Intel Corporation
    Inventors: Tony L. Werner, Aravind Kalaiah, Vijay Korthikanti, Horace Lau
  • Patent number: 10228937
    Abstract: An apparatus may comprise a multi-dimensional memory, a plurality of matrix processors, and a matrix routine memory. The matrix routine memory may store a plurality of programmable matrix routines, wherein each programmable matrix routine comprises a plurality of instructions associated with a particular matrix operation, wherein the plurality of instructions is to be executed by the plurality of matrix processors. Further, the plurality of matrix processors may be configured to: receive a command to perform a matrix operation; receive matrix data from the multi-dimensional memory; extract one or more matrix operands from the matrix data; identify a programmable matrix routine associated with the matrix operation; receive the programmable matrix routine from the matrix routine memory; execute the programmable matrix routine using the one or more matrix operands; and obtain a result of the matrix operation based on execution of the programmable matrix routine.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Tony L. Werner, Aravind Kalaiah, Vijay Korthikanti, Horace Lau
  • Publication number: 20180189057
    Abstract: In one embodiment, a matrix operation may be performed on one or more matrix operands. For example, matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands. The one or more matrix operands may be extracted from the matrix data. A matrix routine associated with the matrix operation may be identified. The matrix routine may be executed on a matrix processor using the one or more matrix operands. A result of the matrix operation may be obtained based on the matrix routine executed by the matrix processor.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Tony L. Werner, Aravind Kalaiah, Vijay Korthikanti, Horace Lau