Abstract: An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to be provided, and hardware logic operates to control how that data is provided. An interrupt vector register is included in the computer CPU. The interrupt vector register does not act like the typical register. It is not a physical register, and cannot be written to. A read to this register by the programmable software, triggers the hardware logic. Once triggered, this logic performs certain control tasks, the end result of which is returning to the programmable software, a vector corresponding to the interrupt having highest priority. The programmable software can implement various software policies, in addition to the hardware policy implemented by the hardware logic.

Abstract: Methods and apparatus are disclosed for determining whether the highest priority pending interrupt is an active level-triggered interrupt. One method includes: determining whether the vector corresponding to the highest priority pending interrupt matches the vector associated with a particular interrupt input; if it does, determining whether that particular interrupt input is programmed to be a level-triggered interrupt; if it is, determining whether the level-status of that particular interrupt input is active; and, if it is, sending a level-triggered active message for the highest priority pending interrupt, by maintaining the set status of a particular bit.