Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: An information handling system includes a processor, a controller hub, a shared higher bandwidth path coupling the processor to the controller hub, and an exclusive lower bandwidth path coupling the processor to the controller hub. The processor communicates system management information over the bandwidth path in response to a first set of criteria and communicates the information over the lower bandwidth path in response to the second set of criteria.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: A wireless charging module includes an antenna and a wireless charger module. An enclosure is configured to fit at least partially within an optical drive bay of an information handling system. The antenna is disposed within a plastic lower portion of the enclosure. The plastic lower portion of the enclosure is configured to enable the antenna to wirelessly receive power from a wireless charging pad. The wireless charger module is disposed within the enclosure, and is configured to provide power to the information handling system.

Abstract: An information handling system includes a processor, a controller hub, a shared higher bandwidth path coupling the processor to the controller hub, and an exclusive lower bandwidth path coupling the processor to the controller hub. The processor communicates system management information over the bandwidth path in response to a first set of criteria and communicates the information over the lower bandwidth path in response to the second set of criteria.

Abstract: An information handling system includes a processor, a controller hub, a shared higher bandwidth path coupling the processor to the controller hub, and an exclusive lower bandwidth path coupling the processor to the controller hub. The processor communicates system management information over the bandwidth path in response to a first set of criteria and communicates the information over the lower bandwidth path in response to the second set of criteria.

Abstract: An information handling system includes a set of power and performance profiles. Based on which of the profiles has been selected, the information handling system selects a thread scheduling table for provision to an operating system. The thread scheduling table determines the sequence of processor cores at which program threads are scheduled for execution. In a power-savings mode, the corresponding thread scheduling table provides for threads to be concentrated at subset of available processor cores, increasing the frequency with which the information handling system can place unused processors in a reduced power state.

Abstract: An information handling system includes a processor, a controller hub, a shared higher bandwidth path coupling the processor to the controller hub, and an exclusive lower bandwidth path coupling the processor to the controller hub. The processor communicates system management information over the bandwidth path in response to a first set of criteria and communicates the information over the lower bandwidth path in response to the second set of criteria.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: A method for managing performance and power utilization of a processor in an information handling system (IHS) employing a balanced fully-multithreaded load threshold is disclosed. The method includes providing a maximum current thread utilization (Umax) and a minimum current thread utilization (Umin) among all current thread utilizations of the processor and determining a current performance state (P state) of the processor. The method also includes increasing a current P state of the processor to a next P state of the processor towards a maximum P state (Pmax) of the processor when the current P state of the processor is between Umax and Umin and the current utilization rate of the processor is less than a first threshold utilization rate. The method further includes engaging the processor in a turbo mode when the current P state of the processor reaches the Pmax and the current utilization of the processor is greater than the first threshold utilization rate of the processor.

Abstract: In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.

Abstract: Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.

Abstract: A system and method is disclosed for providing memory performance states in a computing system. The operating system power management component of the computing system establishes a set of performance states, with each performance state being defined by a number of factors, including the core frequency of memory. The operating system power management component also defines the number of memory performance states that are supported by the computing system and the number of supported memory performance states that are available for use by the computing system. Whether a supported memory performance state is available is dependent upon a measure of the power being consumed by the computing system, the thermal output of the computing system, or both measures.

Abstract: A method for dynamically adjusting performance states of a processor includes executing a workload associated with a workload mode and determining a primary thread among all processor threads executing the workload. The method also includes calculating and setting a performance state (P state) of the processor based on the workload mode.

Abstract: An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS.

Abstract: Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.

Abstract: An information handling system includes a first processor device to execute a handler in response to a system management interrupt (SMI). While the first processor device executes the SMI handler, a second processor device of the information handling system can continue to execute software and perform other operations in a normal mode. When the first processor device accesses a shared resource in executing the SMI handler, an SMI trap for the shared resource is enabled. In response to the second processor device triggering the SMI trap by accessing the shared resource, the second processor device enters an SMI mode, thereby suspending execution of software and other operations. Accordingly, a second processor device is allowed to continue normal operations while a first processor device executes an SMI handler, improving system efficiency while preventing shared resource conflicts.

Abstract: In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.

Abstract: A system and method is disclosed for managing system management interrupts in a multiprocessor system. The system described herein includes multiple processors, each of which may be directly coupled to memory. A primary processor will recognize the initiation of a system management interrupt. The primary processor will write a reason code to a storage location and set a watchdog timer, the expiration of which causes all of the processors of the system to enter a system management mode. After all of the processors have entered system management mode, it is determined if the reason code of the storage location corresponds to certain software-based system management interrupts. If so, the system management interrupt is handled by the local processors. Following the handling of the system management interrupt by the local processor, a signal is sent to each of the other processors to cause the processors to exit system management mode.