Patents by Inventor Vijay Parthasarathy
Vijay Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080197397Abstract: In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee, Martin H. Manley
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Publication number: 20080197406Abstract: In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee, Martin H. Manley
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Patent number: 7368786Abstract: Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.Type: GrantFiled: March 11, 2005Date of Patent: May 6, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Hongzhong Xu, Richard T. Ida, Vijay Parthasarathy
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Patent number: 7355260Abstract: A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.Type: GrantFiled: June 30, 2004Date of Patent: April 8, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose
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Patent number: 7309638Abstract: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.Type: GrantFiled: July 14, 2005Date of Patent: December 18, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose, Todd C. Roggenbauer
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Patent number: 7282386Abstract: A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.Type: GrantFiled: April 29, 2005Date of Patent: October 16, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose
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Publication number: 20070239866Abstract: A method and system for increasing the computational and network efficiency of presence servers having collections of publications is provided. The presence system uses several techniques that enable a presence server to provide rich presence information without requiring expensive processing. First, the presence system accepts batches of publication updates in a single presence update request. Similarly, the presence system accepts batches of subscription requests. Next, the presence system supports new expiration types for publication update requests that eliminate the need for a publishing user to continually refresh presence information that has not changed. Finally, the presence system accepts access lists that contain membership groups rather than an individual list of users that are to have access to a particular presence collection.Type: ApplicationFiled: March 31, 2006Publication date: October 11, 2007Applicant: Microsoft CorporationInventors: Shaun Cox, Serkan Kutan, Timothy Rang, Vijay Parthasarathy
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Patent number: 7247003Abstract: A stacked ceramic matrix composite lamellate assembly (10) including shear force bearing structures (48) for resisting relative sliding movement between adjacent lamellae. The shear force bearing structures may take the form of a cross-lamellar stitch (50), a shear pin (62), a warp (90) in the lamellae, a tongue (104) and groove (98) structure, or an inter-lamellar sealing member (112), in various embodiments. Each shear force bearing structure secures a subset of the lamellae, with at least one lamella being common between adjacent subsets in order to secure the entire assembly.Type: GrantFiled: January 7, 2005Date of Patent: July 24, 2007Assignee: Siemens Power Generation, Inc.Inventors: Michael A. Burke, Jay A. Morrison, Steven James Vance, Daniel G. Thompson, Vijay Parthasarathy, Gary B. Merrill, Douglas Allen Keller
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Patent number: 7141860Abstract: An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.Type: GrantFiled: June 23, 2004Date of Patent: November 28, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Vishnu K. Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose
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Publication number: 20060246670Abstract: A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.Type: ApplicationFiled: April 29, 2005Publication date: November 2, 2006Applicant: Freescale Semiconductor, Inc.Inventors: Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose
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Publication number: 20060244081Abstract: In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).Type: ApplicationFiled: June 27, 2006Publication date: November 2, 2006Applicant: Freescale Semiconductor, Inc.Inventors: Ronghua Zhu, Amitava Bose, Vishnu Khemka, Vijay Parthasarathy
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Publication number: 20060202265Abstract: Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.Type: ApplicationFiled: March 11, 2005Publication date: September 14, 2006Inventors: Hongzhong Xu, Richard Ida, Vijay Parthasarathy
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Patent number: 7095092Abstract: In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).Type: GrantFiled: April 30, 2004Date of Patent: August 22, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Ronghua Zhu, Amitava Bose, Vishnu K. Khemka, Vijay Parthasarathy
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Patent number: 7071518Abstract: A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.Type: GrantFiled: May 28, 2004Date of Patent: July 4, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Vijay Parthasarathy, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose
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Publication number: 20060120874Abstract: A stacked ceramic matrix composite lamellate assembly (10) including shear force bearing structures (48) for resisting relative sliding movement between adjacent lamellae. The shear force bearing structures may take the form of a cross-lamellar stitch (50), a shear pin (62), a warp (90) in the lamellae, a tongue (104) and groove (98) structure, or an inter-lamellar sealing member (112), in various embodiments. Each shear force bearing structure secures a subset of the lamellae, with at least one lamella being common between adjacent subsets in order to secure the entire assembly.Type: ApplicationFiled: January 7, 2005Publication date: June 8, 2006Inventors: Michael Burke, Jay Morrison, Steven Vance, Daniel Thompson, Vijay Parthasarathy, Gary Merrill, Douglas Keller
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Publication number: 20060014342Abstract: A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.Type: ApplicationFiled: July 14, 2005Publication date: January 19, 2006Applicant: Freescale Semiconductor, Inc.Inventors: Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose, Todd Roggenbauer
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Publication number: 20060001057Abstract: A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Inventors: Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose
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Publication number: 20050285188Abstract: An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.Type: ApplicationFiled: June 23, 2004Publication date: December 29, 2005Inventors: Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, Amitava Bose
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Publication number: 20050275055Abstract: A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.Type: ApplicationFiled: May 28, 2004Publication date: December 15, 2005Inventors: Vijay Parthasarathy, Vishnu Khemka, Ronghua Zhu, Amitava Bose
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Publication number: 20050245020Abstract: In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).Type: ApplicationFiled: April 30, 2004Publication date: November 3, 2005Inventors: Ronghua Zhu, Amitava Bose, Vishnu Khemka, Vijay Parthasarathy