Abstract: A capacitor charging circuit is provided with a primary side output voltage sensing circuit for generating a control signal indicative of whether the output voltage has reached a desired level. The control signal is unaffected by voltage spikes occurring when the main switch is turned off. In one embodiment, the circuit filters the primary side voltage for comparison to a reference voltage in order to provide the control signal. In another embodiment, an AND gate provides the control signal indicating that the output voltage has reached the desired level only in response to the primary side voltage being greater than a reference voltage and the secondary current being discontinuous. In a further embodiment, an AND gate provides the control signal indicating that the output voltage has reached the desired levels only in response to a predetermined delay occurring after the primary side voltage becomes greater than a reference voltage and the secondary current being discontinuous.

Abstract: The present invention is a method and apparatus to synchronize multiple switching regulators in out of phase mode without a phase locked loop. In the present invention, each multiple slave device is connected to a master device and to one another in series, as well as connected to a master clock signal. After a DH, LX or DL output from a preceding device is detected by a following connected slave device, the first subsequent edge of a master clock signal serves to reset the internal clock of the slave device. Each slave device in turn, drives a separate power MOSFET pair in out of phase mode, based upon the output of the preceding device and synchronized to the master clock signal. In the case of multiple regulators, synchronization may be used to reduce electronic noise levels or confine noise to known non-sensitive frequency bands.