Patents by Inventor Vijay S. Iyengar
Vijay S. Iyengar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190172564Abstract: A system may predict costs for a set of members by building and using a predictive pipeline. The pipeline may be built using a set of historical data for training members. A set of member-level features can be identified by performing empirical testing on the set of historical data. The trained configurable predictive pipeline can generate a set of predictive data for each member, using historical test data for a set of testing members. The system can then generate a predictive report for each set of predictive data.Type: ApplicationFiled: December 5, 2017Publication date: June 6, 2019Inventors: Rachita Chandra, Vijay S. Iyengar, Dmitriy A. Katz, Karthikeyan Natesan Ramamurthy, Emily A. Ray, Moninder Singh, Dennis Wei, Gigi Y. C. Yuen-Reed, Kevin N. Tran
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Publication number: 20140257846Abstract: Detecting fraud in the health care industry includes selecting a given focus scenario (e.g., prescription rate in a certain drug therapeutic class) for audit analysis, and constructing baseline models with the appropriate normalizations to describe the expected behavior within the focus area. These baseline models are then used, in conjunction with statistical hypothesis testing, to identify entities whose behavior diverges significantly from their expected behavior according to the baseline models. A Likelihood Ratio (LR) score over the relevant claims with respect to the baseline model is obtained for each entity, and the p-value significance of this score is evaluated to ensure that the abnormal behavior can be identified at the specified level of statistical significance. The approach may be used as part of a preliminary computer-aided audit process in which the relevant entities with the abnormal behavior are identified with high selectivity for a subsequent human-intensive audit investigation.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: International Business Machines CorporationInventors: Keith B. Hermiz, Vijay S. Iyengar, Ramesh Natarajan
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Publication number: 20140257832Abstract: Detecting fraud in the health care industry includes selecting a given focus scenario (e.g., prescription rate in a certain drug therapeutic class) for audit analysis, and constructing baseline models with the appropriate normalizations to describe the expected behavior within the focus area. These baseline models are then used, in conjunction with statistical hypothesis testing, to identify entities whose behavior diverges significantly from their expected behavior according to the baseline models. A Likelihood Ratio (LR) score over the relevant claims with respect to the baseline model is obtained for each entity, and the p-value significance of this score is evaluated to ensure that the abnormal behavior can be identified at the specified level of statistical significance. The approach may be used as part of a preliminary computer-aided audit process in which the relevant entities with the abnormal behavior are identified with high selectivity for a subsequent human-intensive audit investigation.Type: ApplicationFiled: September 17, 2013Publication date: September 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith B. Hermiz, Vijay S. Iyengar, Ramesh Natarajan
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Patent number: 7343272Abstract: A system for detecting clusters in space and time using input data on occurrences of a phenomenon and characteristics at a plurality of locations and times comprises an expectation generation module determining expected occurrences of a phenomena, and an occurrence modeling module determining actual occurrences of the phenomena. The system further comprises a search module searching the expected occurrences and the actual occurrences for a plurality of candidate solutions, wherein each solution is represented as a set of points in the three-dimensional space, and wherein each point corresponds to a location at a time. The system comprises a convex container module determining at least one solution corresponding to a selected convex container shape from the plurality of candidate solutions, and a solution evaluation module determining a strength metric for each solution determined by the convex container module, the search module selecting a dominant cluster in the input data.Type: GrantFiled: February 12, 2004Date of Patent: March 11, 2008Assignee: International Business Machines CorporationInventor: Vijay S. Iyengar
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Patent number: 7024409Abstract: A data transform system comprises a processor, a memory connected to the processor, storing a collection of data, and a data transform module, accepting two data constraints and the collection of data from memory, wherein a first constraint is a usage constraint and a second constraint is a privacy constraint, the data transform module transforming the collection of data according to the usage constraint and the privacy constraint.Type: GrantFiled: April 16, 2002Date of Patent: April 4, 2006Assignee: International Business Machines CorporationInventor: Vijay S. Iyengar
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Patent number: 6721737Abstract: A method is provided for ranking a plurality of items. The method comprises initializing a (D−1) dimensional weight space including a feasible region, where D is equal to a number of attributes and a point in the weight space corresponds to each attribute, determining an item pair, and querying a user to select an item from among the item pair. The method further includes reducing the feasible region based upon a user's item selection, and ranking the items according a ranking point in a reduced feasible region. The ranking point is a center of the reduced feasible region, wherein the center is one of a vertex barycenter and center of gravity. The ranking point corresponds to a users item selection. The method includes the step of selecting a plurality of hyperplanes, each hyperplane corresponding to an item pair such that the hyperplane divides the feasible region into two substantially equal portions.Type: GrantFiled: April 4, 2001Date of Patent: April 13, 2004Assignee: International Business Machines CorporationInventors: Vijay S. Iyengar, Jonathan Lee
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Publication number: 20030208457Abstract: A data transform system comprises a processor, a memory connected to the processor, storing a collection of data, and a data transform module, accepting two data constraints and the collection of data from memory, wherein a first constraint is a usage constraint and a second constraint is a privacy constraint, the data transform module transforming the collection of data according to the usage constraint and the privacy constraint.Type: ApplicationFiled: April 16, 2002Publication date: November 6, 2003Applicant: International Business Machines CorporationInventor: Vijay S. Iyengar
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Publication number: 20020165859Abstract: A method is provided for ranking a plurality of items. The method comprises initializing a (D−1) dimensional weight space including a feasible region, where D is equal to a number of attributes and a point in the weight space corresponds to each attribute, determining an item pair, and querying a user to select an item from among the item pair. The method further includes reducing the feasible region based upon a user's item selection, and ranking the items according a ranking point in a reduced feasible region. The ranking point is a center of the reduced feasible region, wherein the center is one of a vertex barycenter and center of gravity. The ranking point corresponds to a users item selection. The method includes the step of selecting a plurality of hyperplanes, each hyperplane corresponding to an item pair such that the hyperplane divides the feasible region into two substantially equal portions.Type: ApplicationFiled: April 4, 2001Publication date: November 7, 2002Applicant: International Business Machines CorporationInventors: Vijay S. Iyengar, Jonathan Lee
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Patent number: 4763289Abstract: A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.Type: GrantFiled: December 31, 1985Date of Patent: August 9, 1988Assignee: International Business Machines CorporationInventors: Zeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman
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Patent number: 4727313Abstract: A method of simulating a differential cascode voltage switch circuit (domino circuit) by replacing each switch-level logic tree by a three-section Boolean tree. In each section, a switch is replaced by an AND gate. The first and third section pass signals in one direction and the second section passes signals in the opposite directions. The three sections are interconnected end to end. Various faults can be simulated by holding selected internal signals at faulty values.Type: GrantFiled: March 8, 1985Date of Patent: February 23, 1988Assignee: International Business Machines CorporationInventors: Zeev Barazilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman
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Patent number: 4698830Abstract: A shift register latch (SRL) arrangement for testing a combinational logic circuit, producing true and complement outputs in nature, has two clocked DC latches and additional circuitry for providing an input to the second latch. Clock signal trains and an extra TEST signal are used to control the SRL arrangement in different modes. In a first mode, one of the outputs from the combinational logic circuit is latched into the first latch and provided to a succeeding combinational logic circuit. In a second mode, a plurality of the SRL arrangements are interconnected together to form a shift register chain so that each latch acts as one position of the shift register chain. Further, in a third mode, the true and complement outputs of the combinational logic circuit are exclusive ORed and its result is latched into the second latch. During the third mode, output of the first latch is prevented from being latched into the second latch.Type: GrantFiled: April 10, 1986Date of Patent: October 6, 1987Assignee: International Business Machines CorporationInventors: Zeev Barzilai, Vijay S. Iyengar, Gabriel M. Silberman