Patents by Inventor Vijay S.R. Degalahal

Vijay S.R. Degalahal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190041970
    Abstract: In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.
    Type: Application
    Filed: September 26, 2018
    Publication date: February 7, 2019
    Inventors: Vijay S. R. Degalahal, Pronay Dutta, Robert Gough, Panner Kumar, Chia-Hung Kuo, Karthi Vadivelu
  • Publication number: 20190011976
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 13, 2018
    Publication date: January 10, 2019
    Applicant: Intel Corporation
    Inventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S. R. Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
  • Patent number: 10114448
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S R Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
  • Publication number: 20160004296
    Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: Intel Corporation
    Inventors: JAWADH HAJ-YIHIA, ELIEZER WEISSMANN, VIJAY S R DEGALAHAL, NADAV SHULMAN, TAL KUZI, ITAY FRANKO, AMIT GUR, EFRAIM ROTEM
  • Patent number: 8984311
    Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Jaideep Moses, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S. R. Degalahal
  • Publication number: 20140281634
    Abstract: Methods and apparatus relating to controlling power consumption by a Power Supply Unit (PSU) during idle state are described. In one embodiment, a power supply unit enters a lower power consumption state (e.g. S9) based on power state information, corresponding to one or more components of the platform, and comparison of a first value (corresponding to a frequency/frequentness of entry into the lower power consumption state) to a first threshold value. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Inventors: EFRAIM ROTEM, BENJAMIN J. GOULD, JAMES G. HERMERDING, II, JORGE P. RODRIGUEZ, ALON NAVEH, NIR ROSENZWEIG, VIJAY S. R. DEGALAHAL
  • Publication number: 20120173907
    Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Inventors: Jaideep MOSES, Rameshkumar G. Illikkal, Ravishankar Iyer, Jared E. Bendt, Sadagopan Srinivasan, Andrew J. Herdrich, Ashish V. Choubal, Avinash N. Ananthakrishnan, Vijay S.R. Degalahal