Abstract: Microelectronic packages may be formed using the co-deposition of carbon nanotubes. The carbon nanotubes may be functionalized to have an appropriate charge so they can be combined with other materials to give suitable properties. The other materials that are co-deposited may include metals, ceramics, and polymers. The electronic package components may be formed including thermal interface materials, vias, trenches, capacitors, memories, substrates, and substrate cores, as a few examples.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

Abstract: A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

Abstract: Smart curing by coupling a catalyst to one or more surface(s) of one or more microelectronic element(s) is generally described. In this regard, according to one example embodiment, a catalyst is coupled to one or more surface(s) of one or more microelectronic element(s) to promote polymerization of an adhesive brought in contact with the catalyst.

Abstract: A microelectronic package includes a substrate (110) having a first die (120) and a second die (130) located thereon, a first thermal interface material (121) located over the first die, and a second thermal interface material (131) located over the second die. The first thermal interface material has a first set of characteristics, the second thermal interface material has a second set of characteristics, and the first set of characteristics is not identical to the second set of characteristics.

Abstract: Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics.

Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.

Abstract: A system for underfilling in a chip package includes an underfill mixture that ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In one embodiment, the system includes an underfill mixture that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a flip-chip package that uses an underfill mixture.

Abstract: A system for underfilling in a chip package includes an underfill mixture that ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In one embodiment, the system includes an underfill mixture that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a flip-chip package that uses an underfill mixture.

Abstract: A system for underfilling in a chip package includes an underfill mixture that ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In one embodiment, the system includes an underfill mixture that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a flip-chip package that uses an underfill mixture.