Patents by Inventor Vijay Sivasankaran
Vijay Sivasankaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954366Abstract: Providing constant fixed commands to memory dies within a data storage device may result in hardware and firmware overheads impacting the performance at a flash interface module (FIM) because the FIM has to handle both the constant fixed commands and the overheads associated with the constant fixed commands. To avoid the impact on performance at the FIM, multiple fixed commands may be combined into individual multi-commands that may be provided to the memory dies. The use of multi-commands reduces hardware and firmware overheads at the FIM relative to the constant fixed commands, which improves performance of the data storage device because the saturation of the FIM is decreased.Type: GrantFiled: May 26, 2022Date of Patent: April 9, 2024Assignee: Western Digital Technologies, Inc.Inventors: Dinesh Kumar Agarwal, Vijay Sivasankaran, Mikhail Palityka
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Publication number: 20240103762Abstract: Processing commands received from a host computing device by a storage device can require a large amount of processing overhead. This demand for ever greater processing power increases as the size of storage devices increase. Traditional methods have added an increasing number of processors or CPUs to handle these requirements. However, by utilizing a fast path accelerated processing pipeline, additional processors may not be necessary. An accelerated processing pipeline can be configured to bypass one or more steps that are required by non-priority processing pipelines. Each received command can be parsed to determine if it is suitable for accelerated processing. The command can be required to access data in a limited region of the memory device, or to have any data necessary to process the command already in a cache memory. Upon completion of verifications, commands can be placed in a priority queue that is processed before a non-priority queue.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Vijay Sivasankaran, Dinesh Agarwal, Mikhail Palityka
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Patent number: 11941273Abstract: Variable Capacity Zone Namespace (ZNS) Flash Storage Data Path. In one example, a data storage device including an electronic processor that, when executing a variable capacity scheme, is configured to determine whether a special indication regarding a particular zone in a ZNS is received, delay an association of a final flash block with the particular zone, receive and stage host data for the particular zone in a staging area, receive a zone close request, compact the host data with other host data for storage in other zones into second host data, and move the second host data to the final flash block that is associated with the particular zone and the other zones. The compaction of the host data with the other host data into the second host data reduces or eliminates padding in the final flash block, and consequently, reduces overhead in the data storage device.Type: GrantFiled: May 12, 2022Date of Patent: March 26, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11935609Abstract: Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.Type: GrantFiled: May 12, 2022Date of Patent: March 19, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Man Lung Mui, Sahil Sharma
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Publication number: 20240078184Abstract: The present disclosure generally relates to utilizing a transparent host memory buffer (HMB) where the host device is granted access to the HMB to obtain data from a mapping table. The data storage device stores the mapping table in HMB and then allows the host device to view the mapping table and retrieve information. The host device sends a command to the data storage device that includes not only a read command, but also mapping table info specific to the read command. Additionally, an indication of the mapping table version from where the information is also provided. The data storage device, upon receiving the command, confirms the version of the information is the most recent version and then, if confirmed, utilizes the mapping information provided with the command. In so doing, accessing the HMB after receiving the command will not be necessary.Type: ApplicationFiled: July 25, 2023Publication date: March 7, 2024Applicant: Western Digital Technologies, Inc.Inventor: Vijay SIVASANKARAN
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Publication number: 20240078039Abstract: Zone Write Groups (ZWGs) to assist data storage devices and host devices with data recovery. In one embodiment, a data storage device includes a memory storing a Zoned NameSpace (ZNS). The ZNS includes a ZWG including host zones and parity zones. An interface connects the data storage device with a host device. The data storage device includes a data storage device controller including an electronic processor and a memory. The data storage device controller populates the ZWG with buffers received from the host device. The data storage device controller detects corrupted data associated with the ZNS and requests one or more buffers stored in the ZWG. Once the data storage device controller receives the one or more buffers from the ZWG, the data storage device controller performs a recovery event with the one or more buffers.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Vijay Sivasankaran, Oleg Kragel
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Patent number: 11922036Abstract: Host data stream assignment with space-leveling across storage block containers. In one example, a data storage device including an electronic processor that, when executing a space-leveling scheme, is configured to receive a first host data stream, store the first host data stream in a block container assignment queue (BCAQ), detect a next storage block container switching event, responsive to detecting the next storage block container switching event, randomly select a location of the BCAQ, responsive to randomly selecting the location of the BCAQ, assign a second host data stream located at the location of the BCAQ that is selected to a storage block container of a memory, and control the memory to store the second host data stream in the storage block container that is assigned.Type: GrantFiled: May 12, 2022Date of Patent: March 5, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11880604Abstract: Read Fused Groups with uniform resource allocation. In one example, a data storage device including an electronic processor that, when executing the Uniform Read Fused Group scheme, is configured to receive information indicating each zone of a plurality of Zone Namespace (ZNS) zones is assigned to one of a plurality of Read Fused Groups (RFGs), assign a portion of a plurality of resources of a memory to the plurality of ZNS zones, control all of the plurality of concurrency units to process a first resource of the plurality of resources assigned to a first Read Fused Group (RFG) of the plurality of RFGs. The first resource is assigned to a first zone of the plurality of ZNS zones, the first zone is assigned to the first RFG, and the electronic processor is one of the plurality concurrency units.Type: GrantFiled: May 12, 2022Date of Patent: January 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11874770Abstract: An indexless logical-to-physical translation table (L2PTT). In one example, the data storage device including a memory, a data storage controller, and a bus. The memory including a mapping unit staging page that includes a plurality of mapping unit pages and a mapping unit page directory. The data storage controller including a data storage controller memory and coupled to the memory, the data storage controller memory including an indexless logical-to-physical translation table (L2PTT). The bus for transferring data between the data storage controller and a host device in communication with the data storage controller. The data storage controller is configured to perform one or more memory operations with the indexless L2PTT.Type: GrantFiled: May 12, 2022Date of Patent: January 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran
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Publication number: 20230384974Abstract: Providing constant fixed commands to memory dies within a data storage device may result in hardware and firmware overheads impacting the performance at a flash interface module (FIM) because the FIM has to handle both the constant fixed commands and the overheads associated with the constant fixed commands. To avoid the impact on performance at the FIM, multiple fixed commands may be combined into individual multi-commands that may be provided to the memory dies. The use of multi-commands reduces hardware and firmware overheads at the FIM relative to the constant fixed commands, which improves performance of the data storage device because the saturation of the FIM is decreased.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Dinesh Kumar Agarwal, Vijay Sivasankaran, Mikhail Palityka
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Publication number: 20230367500Abstract: Variable Capacity Zone Namespace (ZNS) Flash Storage Data Path. In one example, a data storage device including an electronic processor that, when executing a variable capacity scheme, is configured to determine whether a special indication regarding a particular zone in a ZNS is received, delay an association of a final flash block with the particular zone, receive and stage host data for the particular zone in a staging area, receive a zone close request, compact the host data with other host data for storage in other zones into second host data, and move the second host data to the final flash block that is associated with the particular zone and the other zones. The compaction of the host data with the other host data into the second host data reduces or eliminates padding in the final flash block, and consequently, reduces overhead in the data storage device.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Publication number: 20230368857Abstract: Embodiments described herein provide a linked XOR flash data protection scheme for data storage devices. In particular, the embodiments described herein provide a data storage controller with a memory space efficient XOR-based flash data protection/recovery algorithm with minimal flash block space overhead and support of recovery from full plane failure with neighbor planes disturb (NPD) in a single word line. Additionally, the embodiments described herein provide a reduced flash block space dedicated for XOR parity buffers storage by a factor of a number of planes per die without losing the capability to recover from NPD.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Oleg Kragel, Vijay Sivasankaran, Man Lung Mui, Sahil Sharma
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Publication number: 20230367707Abstract: An indexless logical-to-physical translation table (L2PTT). In one example, the data storage device including a memory, a data storage controller, and a bus. The memory including a mapping unit staging page that includes a plurality of mapping unit pages and a mapping unit page directory. The data storage controller including a data storage controller memory and coupled to the memory, the data storage controller memory including an indexless logical-to-physical translation table (L2PTT). The bus for transferring data between the data storage controller and a host device in communication with the data storage controller. The data storage controller is configured to perform one or more memory operations with the indexless L2PTT.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Oleg Kragel, Vijay Sivasankaran
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Publication number: 20230367512Abstract: Read Fused Groups with uniform resource allocation. In one example, a data storage device including an electronic processor that, when executing the Uniform Read Fused Group scheme, is configured to receive information indicating each zone of a plurality of Zone Namespace (ZNS) zones is assigned to one of a plurality of Read Fused Groups (RFGs), assign a portion of a plurality of resources of a memory to the plurality of ZNS zones, control all of the plurality of concurrency units to process a first resource of the plurality of resources assigned to a first Read Fused Group (RFG) of the plurality of RFGs. The first resource is assigned to a first zone of the plurality of ZNS zones, the first zone is assigned to the first RFG, and the electronic processor is one of the plurality concurrency units.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Publication number: 20230367499Abstract: Host data stream assignment with space-leveling across storage block containers. In one example, a data storage device including an electronic processor that, when executing a space-leveling scheme, is configured to receive a first host data stream, store the first host data stream in a block container assignment queue (BCAQ), detect a next storage block container switching event, responsive to detecting the next storage block container switching event, randomly select a location of the BCAQ, responsive to randomly selecting the location of the BCAQ, assign a second host data stream located at the location of the BCAQ that is selected to a storage block container of a memory, and control the memory to store the second host data stream in the storage block container that is assigned.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11803333Abstract: Read Fused Groups with uniform resource allocation. In one example, a data storage device including an electronic processor that, when executing the Uniform Read Fused Group scheme, is configured to receive information indicating each zone of a plurality of Zone Namespace (ZNS) zones is assigned to one of a plurality of Read Fused Groups (RFGs), assign a portion of a plurality of resources of a memory to the plurality of ZNS zones, control all of the plurality of concurrency units to process a first resource of the plurality of resources assigned to a first Read Fused Group (RFG) of the plurality of RFGs. The first resource is assigned to a first zone of the plurality of ZNS zones, the first zone is assigned to the first RFG, and the electronic processor is one of the plurality concurrency units.Type: GrantFiled: May 12, 2022Date of Patent: October 31, 2023Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11604735Abstract: Aspects of a storage device are provided that allow a controller to leverage cache to minimize occurrence of HMB address overlaps between different HMB requests. The storage device may include a cache and a controller coupled to the cache. The controller may store in the cache, in response to a HMB read request, first data from a HMB at a first HMB address. The controller may also store in the cache, in response to an HMB write request, second data from the HMB at a second HMB address. The controller may refrain from processing subsequent HMB requests in response to an overlap of the first HMB address with an address range including the second HMB address, and the controller may resume processing the subsequent HMB requests after the first data is stored. As a result, turnaround time delays for HMB requests may be reduced and performance may be improved.Type: GrantFiled: December 2, 2021Date of Patent: March 14, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Amir Segev, Dinesh Kumar Agarwal, Vijay Sivasankaran, Nava Eisenstein, Jonathan Journo
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Publication number: 20230017171Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.Type: ApplicationFiled: September 19, 2022Publication date: January 19, 2023Inventors: Oleg Kragel, Xiangyu Tang, Vijay Sivasankaran, Mikhail Palityka
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Patent number: 11449443Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.Type: GrantFiled: February 26, 2021Date of Patent: September 20, 2022Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Xiangyu Tang, Vijay Sivasankaran, Mikhail Palityka
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Publication number: 20220121587Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.Type: ApplicationFiled: February 26, 2021Publication date: April 21, 2022Inventors: Oleg Kragel, Xiangyu Tang, Vijay Sivasankaran, Mikhail Palityka